[libspirv] Have SPIR-V copysign use CLC copysign

[frasercrmck]

This mirrors the OpenCL copysign builtin, and brings benefits in keeping types in vectors as opposed to scalarizing.

[frasercrmck]

Note, CLC copysign was introduced in cfc8ef0 which we pulled in

[frasercrmck]

See an example of the codegen difference for Native CPU:

in function _Z20__spirv_ocl_copysignDv2_DF16_S_:
  in block %entry:
    >   %2 = tail call <2 x half> @llvm.copysign.v2f16(<2 x half> %0, <2 x half> %1)
    >   %3 = bitcast <2 x half> %2 to i32
    >   ret i32 %3
    <   %2 = extractelement <2 x half> %0, i64 0
    <   %3 = extractelement <2 x half> %1, i64 0
    <   %conv.i7.i = fpext half %2 to double
    <   %conv1.i8.i = fpext half %3 to double
    <   %4 = tail call double @llvm.copysign.f64(double %conv.i7.i, double %conv1.i8.i)
    <   %conv2.i9.i = fptrunc double %4 to half
    <   %vecinit.i = insertelement <2 x half> poison, half %conv2.i9.i, i64 0
    <   %5 = extractelement <2 x half> %0, i64 1
    <   %6 = extractelement <2 x half> %1, i64 1
    <   %conv.i.i = fpext half %5 to double
    <   %conv1.i.i = fpext half %6 to double
    <   %7 = tail call double @llvm.copysign.f64(double %conv.i.i, double %conv1.i.i)
    <   %conv2.i.i = fptrunc double %7 to half
    <   %vecinit4.i = insertelement <2 x half> %vecinit.i, half %conv2.i.i, i64 1
    <   %8 = bitcast <2 x half> %vecinit4.i to i32
    <   ret i32 %8

Note also that half was previously promoting to double. This was spotted in #17163.