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[component] Request for Verified Docker Image & Discussion Channel - Persistent Bazel Build/Test Failures for OpenTitan Simulations

Status: Open.

#29164 In lowRISC/opentitan;

· liuyanghu opened on Jan 22, 2026

[util] Removal of python3-urllib3 prevents util/get-toolchain.py from working

Status: Open.

#29143 In lowRISC/opentitan;

· olivierdagenais opened on Jan 16, 2026

[otbn] Expose the <code>INSN_CNT</code> register to OTBN apps

IP:otbn

Status: Open.

Enhancement

#29139 In lowRISC/opentitan;

· andrea-caforio opened on Jan 16, 2026

[bazel] Missing configurations when building FPGA bitstream from scratch

Status: Open.

#29133 In lowRISC/opentitan;

· barguello opened on Jan 15, 2026

[ci] CI runs do not use a Python venv

Component:CIContinuous Integration (Azure Pipelines & Co.)Continuous Integration (Azure Pipelines & Co.)

Type:EnhancementFeature requests, enhancementsFeature requests, enhancements

Status: Open.

#29132 In lowRISC/opentitan;

· AlexJones0 opened on Jan 15, 2026

[python] <code>uv sync</code> fails using a Python 3.14 interpreter

Component:SoftwareIssue related to SoftwareIssue related to Software

Type:BugBugsBugs

Status: Open.

#29131 In lowRISC/opentitan;

· AlexJones0 opened on Jan 15, 2026

[test] Versions of Verilator &gt;= 5.0 require --timing or --no-timing options for top level sim builds

Status: Open.

#29102 In lowRISC/opentitan;

· tom7980 opened on Jan 13, 2026

[ECC] How could I use secded_gen.py script only?

Status: Open.

#29059 In lowRISC/opentitan;

· gao12 opened on Jan 9, 2026

[sival] <code>sleep_pin_wake</code> test should cover all pins in one run

Component:SiliconValidation

Status: Open.

#29055 In lowRISC/opentitan;

· jwnrt opened on Jan 8, 2026

[chip-test] Failing UART Tests due to configuring UART1 pins from IOB4,B5 pins to IOA0,A1 pins

Component:ChipLevelTestUsed to filter the chip-level test backlogUsed to filter the chip-level test backlog

Status: Open.

#29028 In lowRISC/opentitan;

· rprakas-gsc opened on Jan 5, 2026

[otbn, dv] Modelling SW errors during delayed escalation

Component:DVDV issue: testbench, test case, etc.DV issue: testbench, test case, etc.

IP:otbn

Status: Open.

#29026 In lowRISC/opentitan;

· etterli opened on Jan 5, 2026

[earlgrey,otp,bazel] OTP build fails with "invalid OTP address" after modifying top_earlgrey

Status: Open.

#29007 In lowRISC/opentitan;

· minh11-cpu opened on Dec 27, 2025