Guidelines for getting started using HDL Coder to generate VHDL or Verilog to target FPGA or ASIC hardware. The document provides practical guidance for:
- Setting up your MATLAB algorithm or Simulink model for HDL code generation
- How to create HDL-ready Simulink models, Stateflow charts, and MATLAB Function blocks
- Tips and advanced techniques for HDL code generation
- Code generation settings for specific FPGA/SoC targets, including AXI interfaces
- Converting to fixed-point or utilizing native floating-point
- Optimizing for various goals and targets
- Verifying your generated code
Examples are included to illustrate selected concepts.
Copyright 2025, The MathWorks, Inc.