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Sameeranjoshi
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Single commit fix for #1306

  1. Unroll vector.multi_reduction -> vector.reduction and transfer_read/writes -> load/stores
  2. Add correctness support for Reduction tests in run.py
  3. Made the tiling sizes in the copy pipeline to be 32 as they are legalized in Peano.

…enerates vector.extract + vector.add + vector.insert, need vector.transfer_Write instead.
This is partial fix, the program fails for out of Program memory on a core.
1. solves the reduction legalizer issue.
2. Converts the transfer_reads into loads
3. Applies 2D->1D flattening pattern on vector type.
4. Solves stack size problem by bumping the stack size.
1. Selected appropriate tile sizes.
   Peano vectorizes for <32xbf16> we choose the tile sizes such that we always
   generate the legal shapes.
2. found the bounds for both bf16 and f32 which work.
3. Tested the patch and cleaned up the patterns.
F32
 Correctness: Pass
 Benchmark: Fails PM issue(run_benchmarks=true)

BF16:
 Correctness: Fails
 Benchmarks: Pass(but this might be not correct as results are wrong)

Run commands:
python run.py delete_out_reduction $IREE_DIR --xrt_dir=$XRT_DIR --peano_dir=$PEANO_DIR \
--target_device="npu4" --xrt_lite_n_core_rows=$XRT_LITE_N_CORE_ROWS \
--xrt_lite_n_core_cols=$XRT_LITE_N_CORE_COLS --tests Reduction
@newling
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newling commented Aug 8, 2025

Nice! FFR, accompanying peano changes: Xilinx/llvm-aie#604

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2 participants