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Mismatch in CoSpike co-simulation about WLRL CSR registers

Status: Open.

#258 In ucb-bar/testchipip;

· ZhongYic00 opened on Apr 30, 2025

Remove dependency on sifive-blocks

Status: Open.

#156 In ucb-bar/testchipip;

· jerryz123 opened on Jan 18, 2023

It cannot compatible 128 bit data length

Status: Open.

#147 In ucb-bar/testchipip;

· matchchen opened on Jul 11, 2022

Make BlockDevice base address come from Config

Status: Open.

#131 In ucb-bar/testchipip;

· timsnyder-siv opened on Apr 16, 2021

Make SimDRAM work when physical address width > 32 bits.

bug

Status: Open.

#127 In ucb-bar/testchipip;

· jerryz123 opened on Mar 29, 2021

TSI Host Widget Full Integration Test

enhancement

help wanted

Status: Open.

#117 In ucb-bar/testchipip;

· abejgonzalez opened on Jan 8, 2021

TSI Host Widget Documentation

enhancement

help wanted

Status: Open.

#116 In ucb-bar/testchipip;

· abejgonzalez opened on Jan 8, 2021

value += is not a member of String

Status: Open.

#95 In ucb-bar/testchipip;

· apaj opened on Jul 23, 2020

SerialAdapter should require minLatency > 0

Status: Open.

#88 In ucb-bar/testchipip;

· mwachs5 opened on Jun 13, 2020

Use PlusArgArtefacts.append to avoid emulator.cc hacks in next RC bump

Status: Open.

#86 In ucb-bar/testchipip;

· jwright6323 opened on May 21, 2020

Eventually move to the <code>InModuleBody</code> paradigm instead of <code>ModuleImp</code>s to mirror rocket-chip

Status: Open.

#77 In ucb-bar/testchipip;

· jwright6323 opened on Apr 16, 2020

Import issue: compile fails, can't find UARTPortIO

Status: Open.

#72 In ucb-bar/testchipip;

· bradley-evans opened on Mar 24, 2020