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* SinkC: fix bug for regs Buf not init * MSHR: fix bug when L1_acquirePerm but L2_miss, L2 should acquireBlock to L3, not only acquirePerm * MainPipe: when L3_probetoB and L2=TIP, L2 donot need probetoB L1 * SinkB: cannot accept Probe when same-addr Release to L3 and have not receive ReleaseAck --------- Co-authored-by: Cai Luoshan <cailuoshan18@mails.ucas.ac.cn>
* ReqArb: only give s1 info when s1-to-s2 fire * Backbone: new structure for Hint now we send Hint @s1 for every MSHR-GrantData passing by and send Hint @s3 for every CHN-GrantData passing by * CoupledL2: update logic for Hint Arb * misc: fix connection * Hint: consider new feature ** AMergeTask ** * Hint: fix Hint Arb among Slices * Hint: add keyword info
Enter command `make test-top-chil2` to generate CHI-CoupledL2 verilog
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This pull request introduces TL2CHICoupledL2, which adopts TileLink standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification to connect downstream interconnect. The key features of TL2CHICoupledL2 are: Fully coherent Request Node in a CHI interconnect. Coherency granule of 64B cache line. MESI cache coherence model, which is based on TileLink coherence policies. Transition from TL-C transactions to CHI snoopable requests. Transition from TL-UL transactions to CHI non-snoopable requests. Support for ReadNoSnp, ReadNotSharedDirty, ReadUnique, MakeUnique. Support for WriteNoSnp, WriteBackFull, Evict. Support for all the snoops except for SnpDVMOp. Request retry to manage protocol resources. Message transfer across CHI interfaces based on Link Layer Credit. Power aware signaling on the component interface. The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2 still works as default L2 Cache instance in XiangShan processor for now. However, you can switch to TL2CHICoupledL2 by setting EnableCHI Field to true in src/test/scala/chi/TestTop.scala. --------- Co-authored-by: Zhu Yu <yulightenyu@gmail.com> Co-authored-by: Chen Xi <48302201+Ivyfeather@users.noreply.github.com> Co-authored-by: Kumonda221 <kumonda@kucro3.org> Co-authored-by: cyril0124 <211998078@qq.com>
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--------- Co-authored-by: Zhu Yu <yulightenyu@gmail.com> Co-authored-by: Chen Xi <48302201+Ivyfeather@users.noreply.github.com> Co-authored-by: Kumonda221 <kumonda@kucro3.org> Co-authored-by: cyril0124 <211998078@qq.com>
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This pull request introduces TL2CHICoupledL2, which adopts TileLink standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification to connect downstream interconnect. The key features of TL2CHICoupledL2 are:
The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2 still works as default L2 Cache instance in XiangShan processor for now. However, you can switch to TL2CHICoupledL2 by setting
EnableCHIField to true insrc/test/scala/chi/TestTop.scala.