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Add CoupledL2 with CHI interface #145
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* SinkC: fix bug for regs Buf not init * MSHR: fix bug when L1_acquirePerm but L2_miss, L2 should acquireBlock to L3, not only acquirePerm * MainPipe: when L3_probetoB and L2=TIP, L2 donot need probetoB L1 * SinkB: cannot accept Probe when same-addr Release to L3 and have not receive ReleaseAck --------- Co-authored-by: Cai Luoshan <[email protected]>
* ReqArb: only give s1 info when s1-to-s2 fire * Backbone: new structure for Hint now we send Hint @s1 for every MSHR-GrantData passing by and send Hint @s3 for every CHN-GrantData passing by * CoupledL2: update logic for Hint Arb * misc: fix connection * Hint: consider new feature ** AMergeTask ** * Hint: fix Hint Arb among Slices * Hint: add keyword info
Enter command `make test-top-chil2` to generate CHI-CoupledL2 verilog
Merge branch 'master' into chi-coupledl2
Ivyfeather
requested changes
May 8, 2024
Ivyfeather
approved these changes
May 8, 2024
Ivyfeather
approved these changes
May 8, 2024
Ivyfeather
approved these changes
May 10, 2024
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This pull request introduces TL2CHICoupledL2, which adopts TileLink standard to connect L1 DCache/ICache/PTW, and CHI Issue B specification to connect downstream interconnect. The key features of TL2CHICoupledL2 are:
The original CoupledL2 is now renamed to TL2TLCoupledL2. TL2TLCoupledL2 still works as default L2 Cache instance in XiangShan processor for now. However, you can switch to TL2CHICoupledL2 by setting
EnableCHI
Field to true insrc/test/scala/chi/TestTop.scala
.