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Add CoupledL2 with CHI interface #145

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merged 159 commits into from
May 14, 2024
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45e2dcd
backbone: set up parameter system to adapt to tl2chi CoupledL2
linjuanZ Feb 22, 2024
1d52927
backbone: both chi and tl CoupledL2 inherit from CoupledL2Base
linjuanZ Feb 23, 2024
b42c41d
backbone: add framework for CHI links and messages
linjuanZ Feb 26, 2024
9fa1f0b
backbone: implement top logic for CHI-CoupledL2
linjuanZ Feb 27, 2024
a584a16
backbone: set up basic CHI-CoupledL2 framework
linjuanZ Mar 1, 2024
e9d7246
RequestBuffer: fix potential performance bugs
linjuanZ Mar 4, 2024
00d8e01
RXSNP: transform L-Credit handshake to DecoupledIO using queue
linjuanZ Mar 5, 2024
3a4b1c5
LinkLayer: add utility to transform DecoupledIO into ChannelIO
linjuanZ Mar 6, 2024
29b59d4
Bundle: add trait for extra fields that only CHI TaskBundle owns
linjuanZ Mar 6, 2024
79718a4
Common: rewrite TaskBundle
linjuanZ Mar 7, 2024
ca8eadb
Bundle: update HasCHIChannelBits
linjuanZ Mar 12, 2024
8d843c7
An initial version of MainPipe
linjuanZ Mar 20, 2024
270e92a
initial version
yulightenyu Mar 21, 2024
a909f7c
update
yulightenyu Mar 25, 2024
f3d4abd
update MSHR and RXSNP
yulightenyu Mar 26, 2024
37b98e3
add logic of MSHR and RX*
yulightenyu Mar 26, 2024
7ddf596
update ID transfer
yulightenyu Mar 27, 2024
98143b5
clean some compile error
yulightenyu Mar 27, 2024
cdfb2c0
Add TX* channels and their flow control logic
linjuanZ Mar 27, 2024
efaacbc
Slice: Use DecoupledIO instead of ChannelIO as CHI-side IO
linjuanZ Mar 28, 2024
3904dba
fix compile
yulightenyu Mar 29, 2024
04c23b7
Merge branch 'chi-coupledl2-tx' into chi-coupledl2
linjuanZ Mar 31, 2024
ee2622d
Message: complete and fix flit fields
linjuanZ Mar 31, 2024
6cdabb7
L2Param: fix inconsistency of chiselDB availability (#98)
Tang-Haojin Mar 20, 2024
9b15538
Fix some bugs for CPL2 (#99)
cailuoshan Mar 26, 2024
1869ced
New hint design (#101)
Ivyfeather Mar 29, 2024
cd39ec3
Add TestTop for CHI-CoupledL2
linjuanZ Apr 1, 2024
9602328
Message: add RSVDC field in REQ and DAT channel
linjuanZ Apr 1, 2024
8e36f07
LinkLayer: add flatten of flit and its reverse operation
linjuanZ Apr 1, 2024
c7c1edf
LinkLayer: fix field arrangement in CHI flit
linjuanZ Apr 1, 2024
afbfe08
LinkLayer: fix flitpend assignment
linjuanZ Apr 1, 2024
f47a347
RX*: fix DontCare catastrophe
linjuanZ Apr 1, 2024
07f580f
TestTop: exposed CHI ports from TestTop_CHIL2 and pure-synth RTL conf…
Kumonda221-CrO3 Apr 2, 2024
fa6927f
chi Message: aligned CHI params to current test env
Kumonda221-CrO3 Apr 2, 2024
278b18a
MSHR: fix confusion between tl opcode and chi opcode
linjuanZ Apr 3, 2024
5056f3f
Directory: choose other free way when refill way has conflict mshr en…
cailuoshan Apr 2, 2024
3e72bae
LCredit2Decoupled: cannot send credit when reset is asserted
cyril0124 Apr 3, 2024
2e17f40
LinkLayer: improve readability
cyril0124 Apr 3, 2024
f7cca8e
Merge pull request #105 from cyril0124/chi-coupledl2-fix-bug
linjuanZ Apr 3, 2024
f145939
Fix bug for txChannel assignment (#106)
cyril0124 Apr 5, 2024
fdcb4f7
LinkLayer: refactor link handshake logic
linjuanZ Apr 6, 2024
ad4041c
RXDAT: refillBuf should be written when last beat is received
linjuanZ Apr 6, 2024
55d3ce9
MainPipe: fix assignment of `task_s4.valid`
cyril0124 Apr 6, 2024
a7a11e5
MSHR: deal with Comp resp after Evict is sent
cyril0124 Apr 6, 2024
2dc3bb3
MSHR: fix typo
linjuanZ Apr 6, 2024
195ae4f
MSHR: fix `isTXDAT_s3` which should depend on `doRespData`
cyril0124 Apr 6, 2024
450545d
MSHR: pprobe param depends on opcode of CHI-SNP
linjuanZ Apr 6, 2024
fcb912d
RXSNP: rxsnp should be back-pressured when task is blocked
cyril0124 Apr 6, 2024
d4269ed
LinkLayer: drive `TXLINKACTIVEREQ` HIGH only when reset is done
linjuanZ Apr 7, 2024
c726f2e
Bug Fixes and Improve debuggability (#109)
cyril0124 Apr 7, 2024
055d554
MSHR: retry only when both RetryAck and PCrdGrant are received (#110)
linjuanZ Apr 7, 2024
b34185b
chi Messages: realigned the flit width parameters to current NoC conf…
Kumonda221-CrO3 Apr 7, 2024
5b368d7
configs: use hartid from io (#102)
cyyself Apr 7, 2024
09289c5
MSHR: fix assignment of `mp_probeack.txnID` and Add MSHR deadlock det…
cyril0124 Apr 8, 2024
098fb5d
MSHR: fix Retry flow
yulightenyu Apr 8, 2024
bfc22e2
MSHR: clear chi ID info when allocate
yulightenyu Apr 9, 2024
198c11a
MSHR: retry only when both RetryAck and PCrdGrant are received
linjuanZ Apr 7, 2024
796554f
MSHR: Do not promote T for Get
linjuanZ Apr 7, 2024
4b2751f
MSHR: fix opcode of TXREQ task
linjuanZ Apr 8, 2024
78125a7
MSHR: assign WriteBack/Evict and CBWrData separately
linjuanZ Apr 8, 2024
7b80729
MSHR: consider SnpOnce*, SnpStash*, Snp*Fwd for SnpResp* assignment
linjuanZ Apr 8, 2024
f734979
MSHR: fix `dsWen` of Grant task
linjuanZ Apr 9, 2024
bc137f7
MSHR: meta is invalidated only after CBWrData is sent
linjuanZ Apr 9, 2024
ca831b9
MSHR: fix tab chaos
linjuanZ Apr 9, 2024
1fbbbcb
MSHR: fix bug in resp field of RXRSP and RXDAT
linjuanZ Apr 9, 2024
669ebd0
MSHR: CBWrData can only be sent after CompDBIDResp is received
linjuanZ Apr 9, 2024
6bdca14
MSHR: fix bug in MSHR release condition
linjuanZ Apr 9, 2024
3e704c4
Merge pull request #115 from OpenXiangShan/chi-coupledl2-mshr
cyril0124 Apr 9, 2024
f5189aa
MainPipe: read DS when a TRUNK block is snooped
linjuanZ Apr 10, 2024
1c519ea
Merge pull request #117 from OpenXiangShan/chi-coupledl2-fix-probe
cyril0124 Apr 10, 2024
e963cd4
Fix data mismatch bug inside MainPipe and missing assignment of some …
cyril0124 Apr 10, 2024
4dee3c4
NetworkLayer: Add SAM to determine the TgtID of a request
linjuanZ Apr 10, 2024
8c46a51
MSHR: CompAck.TgtID should equal to Comp.SrcID in dataless transaction
linjuanZ Apr 10, 2024
4748cce
MSHRBuffer: initialize buffer to prevent X-state propagation
linjuanZ Apr 10, 2024
01e7058
Revert "MSHRBuffer: initialize buffer to prevent X-state propagation"
linjuanZ Apr 10, 2024
44e09c0
MSHR: set `size` of CopyBack to 64B
linjuanZ Apr 10, 2024
7f72a87
TXREQ: set a fixed value for `size` in TXREQ channel
linjuanZ Apr 11, 2024
5f48c79
MSHR: determine whether to send CBWrData after rprobe is finished
linjuanZ Apr 11, 2024
4083da2
MainPipe: fix assignment of `task_s5.valid`
linjuanZ Apr 11, 2024
a593502
TestTop: fix bug in SAM for CMN 2x2 mesh
linjuanZ Apr 11, 2024
fab9950
Add support for Snp*Fwd
linjuanZ Apr 11, 2024
b95913a
MSHR: fix bugs in protocol retry (#120)
yulightenyu Apr 11, 2024
e83911d
Refactor parameter system
linjuanZ Apr 11, 2024
a249845
configs: fix use hartid from io (#102) (#112)
cyyself Apr 9, 2024
d64991c
Replace `fire()` with `fire` to adapt to Chisel6
linjuanZ Apr 11, 2024
72ee344
GrantBuf: fix bug of inflightGrant overflow (#121)
Archer613 Apr 12, 2024
7fda30c
MSHR: promoteT when req is Get (#123)
cyril0124 Apr 13, 2024
f51be53
backbone: make diplomacy happy
linjuanZ Apr 13, 2024
ae92761
MSHR: use WriteBackFull to replace a block probed to be dirty
linjuanZ Apr 13, 2024
9e18b94
MSHR: use SnpRespData when L1 block is probed to be dirty
linjuanZ Apr 14, 2024
94ef2b9
LinkLayer: set `srcID` of TX channels to hartId from XSTile
linjuanZ Apr 15, 2024
aa546c4
TestTop: add test top for dual cores
linjuanZ Apr 15, 2024
be25f01
TestTop: add ULAgents within each tile
linjuanZ Apr 15, 2024
f27ae67
TXREQ: fix bug in addr of TXREQ when there are multiple slices
linjuanZ Apr 15, 2024
2722118
TestTop: fixed test-scope parameter passing
Kumonda221-CrO3 Apr 15, 2024
4d5b8cc
TestTop: clean up stale codes
linjuanZ Apr 16, 2024
fb7f94d
Add MMIO TileLink-to-CHI Bridge
linjuanZ Apr 16, 2024
01093eb
TestTop: fix bugs in bankBits
linjuanZ Apr 17, 2024
43c688d
MSHRCtrl: fix rxresp.valid when PCrdGrant (#125)
yulightenyu Apr 17, 2024
922ffee
TestTop: Inserted TLBuffer on every upstream TileLink link
Kumonda221-CrO3 Apr 17, 2024
18255c0
RXSNP: fix bug in snoop address parsing
linjuanZ Apr 17, 2024
f413d1a
Handle WriteBackFull-Snoop hazard by nesting Snoops (#126)
linjuanZ Apr 18, 2024
86bcf74
MMIOBridge: add protocol retry for mmio requests
linjuanZ Apr 18, 2024
6c45383
MSHR: add backoff time for replace way retry
linjuanZ Apr 18, 2024
2ff0300
Merge pull request #127 from OpenXiangShan/chi-coupledl2-retry-deadlock
cyril0124 Apr 18, 2024
5a3780c
TL2CHICoupledL2: fix bug in assignment of TXREQ TxnID
linjuanZ Apr 18, 2024
ef0b67f
RXSNP: consider meta hit or not when judging blocking or nesting
linjuanZ Apr 18, 2024
419a2be
RXSNP: fix snoop block condition for alias tasks
linjuanZ Apr 18, 2024
f7a60d5
TL2CIHCoupledL2: fix txnID when PCrdGrant (#128)
yulightenyu Apr 19, 2024
a916046
DataStorage: Adopted SRAM logic to MultiCycle-Path-2
Kumonda221-CrO3 Apr 21, 2024
67df879
RequestArb: Adopted to MultiCycle-Path-2
Kumonda221-CrO3 Apr 21, 2024
71c20b0
L2Param: Added TLLog switching parameter
Kumonda221-CrO3 Apr 22, 2024
4cbbcf2
TestTop: Added TLLog support and L2Param
Kumonda221-CrO3 Apr 22, 2024
849f00c
TestTop: Added test configuration for quad-core CHI-coupledL2
Kumonda221-CrO3 Apr 22, 2024
e8b5a0b
TestTop: fix bug in the width of hartId
linjuanZ Apr 22, 2024
1d0f958
TestTop: Added test configuration for octa-core and hexa-core CHI-cou…
Kumonda221-CrO3 Apr 22, 2024
7e4f0ad
MMIOBridge: fix bug in data arrangement of DAT channel (#130)
linjuanZ Apr 23, 2024
de08b12
MSHR: fix allowRetry bit when release retry (#131)
yulightenyu Apr 24, 2024
52de40e
MainPipe: optimize timing from Directory result directly to TXDAT
linjuanZ Apr 24, 2024
ea3e677
MainPipe: optimize timing for block condition of TXRSP and TXDAT
linjuanZ Apr 24, 2024
0e4fe16
MMIOBridge: fix `reqWordIdx` assignment
linjuanZ Apr 24, 2024
016ecbc
MainPipe: optimize timing from Directory result to GrantBuffer
linjuanZ Apr 24, 2024
a4925ad
Merge pull request #132 from OpenXiangShan/chi-coupledl2-timing
Kumonda221-CrO3 Apr 24, 2024
7eda98b
TL2CHICoupleL2: use Round-Robin when multi-slice hit PCredit (#133)
yulightenyu Apr 25, 2024
673b59f
TL2CHICoupledL2: get RN NodeID from NoC
linjuanZ Apr 25, 2024
50785ac
MMIOBridge: support endpoint order on MMIO space
linjuanZ Apr 26, 2024
fc9a0c3
TestTop: reconstructed and removed redundant configuration
Kumonda221-CrO3 Apr 26, 2024
94c1894
MMIOBridge: disabled byte value in Write Data must be set to zero
linjuanZ Apr 26, 2024
1298dae
RXDAT: write data into RefillBuf every time a beat is received
linjuanZ Apr 27, 2024
b7d3398
MMIOBridge: fix bug in `rxrsp.ready`
linjuanZ Apr 27, 2024
fea7f9c
MSHR: allocate attribute is inapplicable in Evict and must be zero
linjuanZ Apr 28, 2024
f04804c
MSHR: set Order field to zero for all the TXREQ requests
linjuanZ Apr 28, 2024
fd755b5
MSHR, MainPipe: return data when non-fwd snoops hit a BRANCH line
linjuanZ Apr 27, 2024
7de7520
workflows: add CI for compiling check of CHI-CoupledL2 (#135)
linjuanZ Apr 28, 2024
9561e5c
MSHR: return data when `RetToSrc` = 1 and snoop is `SnpUnique*` (#136)
cyril0124 Apr 28, 2024
4477ec2
MSHR & MainPipe: should not assign resp to I_PD when Snoop response i…
cyril0124 Apr 29, 2024
2d6e723
RXSNP: consider Snp nests a WriteBackFull on an invalid block
linjuanZ May 1, 2024
adf2566
TestTop: fixed test configuration passing glitches (#139)
Kumonda221-CrO3 May 1, 2024
d10e28c
Merge pull request #138 from OpenXiangShan/chi-coupledl2-snp-hazard
Kumonda221-CrO3 May 1, 2024
84436b1
MSHR: always refill DS when L2 receives CompData
linjuanZ May 3, 2024
e9cee3c
Merge pull request #140 from OpenXiangShan/chi-coupledl2-fix-dsWen
Kumonda221-CrO3 May 3, 2024
98220de
MSHR, MainPipe: consider snoop nests a Read request (#141)
linjuanZ May 5, 2024
5c3f826
MSHRCtl: change P-credit arbiter from Round-Robin to Random (#142)
yulightenyu May 6, 2024
876a747
RequestArb: restrict concurrent number of Acquires with same set (#143)
linjuanZ May 7, 2024
e9c94b9
Merge branch 'master' into chi-coupledl2-merge-master
linjuanZ May 7, 2024
aa26998
Merge branch 'master' into chi-coupledl2-merge-master
linjuanZ May 7, 2024
5dc3553
workflows: add CI for TL2TLCoupledL2 unit test
linjuanZ May 7, 2024
353fd9e
Merge branch 'chi-coupledl2' into chi-coupledl2-merge-master
linjuanZ May 7, 2024
5c27e6f
Merge pull request #144 from OpenXiangShan/chi-coupledl2-merge-master
Kumonda221-CrO3 May 7, 2024
f5409c5
Prefetcher: temporal prefetch should be optional
linjuanZ May 8, 2024
3f4f8c2
Slice: replenish missing wiring for tlb reqs
linjuanZ May 8, 2024
f95496c
PrefetchReceiver: parameterize temporal prefetch
linjuanZ May 8, 2024
eda60f1
DataStorage: removed registers on data path for MCP2
Kumonda221-CrO3 May 8, 2024
f91969a
MSHR: relaxed deadlock assertion
Kumonda221-CrO3 May 9, 2024
5b5991e
RequestArb: fix bug in `taskInfo_s1` which interferes L1 Hint
linjuanZ May 10, 2024
327d2db
DataStorage: enable holdRead for data sram
linjuanZ May 11, 2024
ee17359
Merge branch 'master' into chi-coupledl2
linjuanZ May 11, 2024
f1f97dd
Delete wrong recursive RegNextN
linjuanZ May 13, 2024
f7e2a78
Merge branch 'master' into chi-coupledl2
linjuanZ May 13, 2024
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12 changes: 8 additions & 4 deletions .github/workflows/main.yml
Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,9 @@ name: CI
on:
# Triggers the workflow on push or pull request events but only for the main branch
push:
branches: [ master, ci-test ]
branches: [ master, chi-coupledl2 ]
pull_request:
branches: [ master, ci-test ]
branches: [ master, chi-coupledl2 ]

# Allows you to run this workflow manually from the Actions tab
workflow_dispatch:
Expand Down Expand Up @@ -47,8 +47,8 @@ jobs:

- name: Compile
run: make compile

- name: Unit test
- name: Unit test for TileLink version
run: |
git clone https://github.com/OpenXiangShan/tl-test -b coupledL2-huancun
make test-top-l2l3l2
Expand All @@ -57,3 +57,7 @@ jobs:
cmake .. -DDUT_DIR=../../build -DCHISELDB=1
make
./tlc_test -s $RANDOM

- name: Compile CHI QuadCore
run: |
make test-top-chi-quadcore-2ul
24 changes: 24 additions & 0 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,30 @@ test-top-l2l3l2:
test-top-fullsys:
mill -i CoupledL2.test.runMain coupledL2.TestTop_fullSys -td build

test-top-chi-dualcore-0ul:
mill -i CoupledL2.test.runMain coupledL2.TestTop_CHI_DualCore_0UL -td build

test-top-chi-dualcore-2ul:
mill -i CoupledL2.test.runMain coupledL2.TestTop_CHI_DualCore_2UL -td build

test-top-chi-quadcore-0ul:
mill -i CoupledL2.test.runMain coupledL2.TestTop_CHI_QuadCore_0UL -td build

test-top-chi-quadcore-2ul:
mill -i CoupledL2.test.runMain coupledL2.TestTop_CHI_QuadCore_2UL -td build

test-top-chi-octacore-0ul:
mill -i CoupledL2.test.runMain coupledL2.TestTop_CHI_OctaCore_0UL -td build

test-top-chi-octacore-2ul:
mill -i CoupledL2.test.runMain coupledL2.TestTop_CHI_OctaCore_2UL -td build

test-top-chi-hexacore-0ul:
mill -i CoupledL2.test.runMain coupledL2.TestTop_CHI_HexaCore_0UL -td build

test-top-chi-hexacore-2ul:
mill -i CoupledL2.test.runMain coupledL2.TestTop_CHI_HexaCore_2UL -td build

clean:
rm -rf ./build

Expand Down
115 changes: 78 additions & 37 deletions src/main/scala/coupledL2/Common.scala
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@ import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.tilelink.TLPermissions._
import utility.MemReqSource
import tl2chi.{HasCHIMsgParameters, HasCHIChannelBits, CHIREQ, MemAttr, OrderEncodings}

abstract class L2Module(implicit val p: Parameters) extends Module with HasCoupledL2Parameters
abstract class L2Bundle(implicit val p: Parameters) extends Bundle with HasCoupledL2Parameters
Expand All @@ -32,7 +33,7 @@ class ReplacerInfo(implicit p: Parameters) extends L2Bundle {
val reqSource = UInt(MemReqSource.reqSourceBits.W)
}

trait HasChannelBits { this: Bundle =>
trait HasTLChannelBits { this: Bundle =>
val channel = UInt(3.W)
def fromA = channel(0).asBool
def fromB = channel(1).asBool
Expand All @@ -52,7 +53,10 @@ class MergeTaskBundle(implicit p: Parameters) extends L2Bundle {

// We generate a Task for every TL request
// this is the info that flows in Mainpipe
class TaskBundle(implicit p: Parameters) extends L2Bundle with HasChannelBits {
class TaskBundle(implicit p: Parameters) extends L2Bundle
with HasTLChannelBits
with HasCHIMsgParameters
with HasCHIChannelBits {
val set = UInt(setBits.W)
val tag = UInt(tagBits.W)
val off = UInt(offsetBits.W)
Expand Down Expand Up @@ -104,9 +108,47 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle with HasChannelBits {
// for merged MSHR tasks(Acquire & late Prefetch)
val mergeA = Bool()
val aMergeTask = new MergeTaskBundle()

// Used for get data from ReleaseBuf when snoop hit with same PA
val snpHitRelease = Bool()
val snpHitReleaseWithData = Bool()
val snpHitReleaseIdx = UInt(mshrBits.W)
// CHI
val tgtID = chiOpt.map(_ => UInt(TGTID_WIDTH.W))
val srcID = chiOpt.map(_ => UInt(SRCID_WIDTH.W))
val txnID = chiOpt.map(_ => UInt(TXNID_WIDTH.W))
val homeNID = chiOpt.map(_ => UInt(SRCID_WIDTH.W))
val dbID = chiOpt.map(_ => UInt(DBID_WIDTH.W))
val fwdNID = chiOpt.map(_ => UInt(FWDNID_WIDTH.W))
val fwdTxnID = chiOpt.map(_ => UInt(FWDTXNID_WIDTH.W))
val chiOpcode = chiOpt.map(_ => UInt(OPCODE_WIDTH.W))
val resp = chiOpt.map(_ => UInt(RESP_WIDTH.W))
val fwdState = chiOpt.map(_ => UInt(FWDSTATE_WIDTH.W))
val pCrdType = chiOpt.map(_ => UInt(PCRDTYPE_WIDTH.W))
val retToSrc = chiOpt.map(_ => Bool()) // only used in snoop
val expCompAck = chiOpt.map(_ => Bool())
val allowRetry = chiOpt.map(_ => Bool())
val memAttr = chiOpt.map(_ => new MemAttr)

def toCHIREQBundle(): CHIREQ = {
val req = WireInit(0.U.asTypeOf(new CHIREQ()))
req.tgtID := tgtID.getOrElse(0.U)
req.srcID := srcID.getOrElse(0.U)
req.txnID := txnID.getOrElse(0.U)
req.opcode := chiOpcode.getOrElse(0.U)
req.addr := Cat(tag, set, 0.U(offsetBits.W))
req.allowRetry := allowRetry.getOrElse(true.B) //TODO: consider retry
req.pCrdType := pCrdType.getOrElse(0.U)
req.expCompAck := expCompAck.getOrElse(false.B)
req.memAttr := memAttr.getOrElse(MemAttr())
req.snpAttr := true.B
req.order := OrderEncodings.None
req
}
}

class PipeStatus(implicit p: Parameters) extends L2Bundle with HasChannelBits
class PipeStatus(implicit p: Parameters) extends L2Bundle
with HasTLChannelBits

class PipeEntranceStatus(implicit p: Parameters) extends L2Bundle {
val tags = Vec(4, UInt(tagBits.W))
Expand All @@ -123,34 +165,6 @@ class PipeEntranceStatus(implicit p: Parameters) extends L2Bundle {
def g_set = sets(3)
}

// MSHR exposes signals to MSHRCtl
class MSHRStatus(implicit p: Parameters) extends L2Bundle with HasChannelBits {
val set = UInt(setBits.W)
val reqTag = UInt(tagBits.W)
val metaTag = UInt(tagBits.W)
val needsRepl = Bool()
val w_c_resp = Bool()
val w_d_resp = Bool()
val will_free = Bool()

// val way = UInt(wayBits.W)
// val off = UInt(offsetBits.W)
// val opcode = UInt(3.W)
// val param = UInt(3.W)
// val size = UInt(msgSizeBits.W)
// val source = UInt(sourceIdBits.W)
// val alias = aliasBitsOpt.map(_ => UInt(aliasBitsOpt.get.W))
// val aliasTask = aliasBitsOpt.map(_ => Bool())
// val needProbeAckData = Bool() // only for B reqs
// val fromL2pft = prefetchOpt.map(_ => Bool())
// val needHint = prefetchOpt.map(_ => Bool())

// for TopDown usage
val reqSource = UInt(MemReqSource.reqSourceBits.W)
val is_miss = Bool()
val is_prefetch = Bool()
}

// MSHR Task that MainPipe sends to MSHRCtl
class MSHRRequest(implicit p: Parameters) extends L2Bundle {
val dirResult = new DirResult()
Expand All @@ -159,11 +173,12 @@ class MSHRRequest(implicit p: Parameters) extends L2Bundle {
}

// MSHR info to ReqBuf and SinkB
class MSHRInfo(implicit p: Parameters) extends L2Bundle {
class MSHRInfo(implicit p: Parameters) extends L2Bundle with HasTLChannelBits {
val set = UInt(setBits.W)
val way = UInt(wayBits.W)
val reqTag = UInt(tagBits.W)
val willFree = Bool()
val aliasTask = aliasBitsOpt.map(_ => Bool())

// to block Acquire for to-be-replaced data until Release done (indicated by ReleaseAck received)
val needRelease = Bool()
Expand All @@ -172,28 +187,42 @@ class MSHRInfo(implicit p: Parameters) extends L2Bundle {
val blockRefill = Bool()

val metaTag = UInt(tagBits.W)
val metaState = UInt(stateBits.W)
val dirHit = Bool()

// decide whether can nest B (req same-addr)
val nestB = Bool()

// to drop duplicate prefetch reqs
val isAcqOrPrefetch = Bool()
val isPrefetch = Bool()

// whether the mshr_task already in mainpipe
val s_refill = Bool()
val param = UInt(3.W)
val mergeA = Bool() // whether the mshr already merge an acquire(avoid alias merge)

val w_grantfirst = Bool()
val s_refill = Bool()
val w_releaseack = Bool()
val w_replResp = Bool()
val w_rprobeacklast = Bool()

val replaceData = Bool() // If there is a replace, WriteBackFull or Evict
}

class RespInfoBundle(implicit p: Parameters) extends L2Bundle {
class RespInfoBundle(implicit p: Parameters) extends L2Bundle
with HasCHIMsgParameters
{
val opcode = UInt(3.W)
val param = UInt(3.W)
val last = Bool() // last beat
val dirty = Bool() // only used for sinkD resps
val isHit = Bool() // only used for sinkD resps
//CHI
val chiOpcode = chiOpt.map(_ => UInt(OPCODE_WIDTH.W))
val txnID = chiOpt.map(_ => UInt(TXNID_WIDTH.W))
val srcID = chiOpt.map(_ => UInt(SRCID_WIDTH.W))
val homeNID = chiOpt.map(_ => UInt(SRCID_WIDTH.W))
val dbID = chiOpt.map(_ => UInt(DBID_WIDTH.W))
val resp = chiOpt.map(_ => UInt(RESP_WIDTH.W))
val pCrdType = chiOpt.map(_ => UInt(PCRDTYPE_WIDTH.W))
}

class RespBundle(implicit p: Parameters) extends L2Bundle {
Expand Down Expand Up @@ -227,6 +256,12 @@ class FSMState(implicit p: Parameters) extends L2Bundle {
val w_grant = Bool()
val w_releaseack = Bool()
val w_replResp = Bool()

// CHI
val s_compack = chiOpt.map(_ => Bool())
val s_cbwrdata = chiOpt.map(_ => Bool())
val s_reissue = chiOpt.map(_ => Bool())
val s_dct = chiOpt.map(_ => Bool())
}

class SourceAReq(implicit p: Parameters) extends L2Bundle {
Expand Down Expand Up @@ -260,7 +295,13 @@ class BlockInfo(implicit p: Parameters) extends L2Bundle {
class NestedWriteback(implicit p: Parameters) extends L2Bundle {
val set = UInt(setBits.W)
val tag = UInt(tagBits.W)
// Nested ReleaseData sets block dirty
val c_set_dirty = Bool()
// Nested Snoop invalidates block
val b_inv_dirty = Bool()

val b_toB = chiOpt.map(_ => Bool())
val b_toN = chiOpt.map(_ => Bool())
}

class PrefetchRecv extends Bundle {
Expand Down
6 changes: 6 additions & 0 deletions src/main/scala/coupledL2/Consts.scala
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,11 @@ object MetaData {
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch

def needB(opcode: UInt, param: UInt): Bool = {
opcode === TLMessages.Get ||
opcode === TLMessages.AcquireBlock && param === TLPermissions.NtoB ||
opcode === TLMessages.Hint && param === TLHints.PREFETCH_READ
}
// Does a request need trunk to be handled?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
Expand Down Expand Up @@ -64,4 +69,5 @@ object MetaData {
Seq(INVALID, INVALID, BRANCH)
)
}
def isValid(state: UInt): Bool = state > INVALID
}
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