v1.1-rc1

Incompatible changes:

• The MHARTID_VAL parameter has been removed, and replaced with the mhartid_val port
• The MIMPID_VAL parameter has been removed
• The mimpid CSR has been redefined to contain the hardcoded Hazard3 release version

New signals:

• fence_i_vld, fence_d_vld and fence_rdy allow external hardware to enforce memory orderings or trigger cache flushes
• mhartid_val allows a dynamic mhartid CSR value
• eco_version allows modifying part of the processor's reported version number in mimpid

New features:

• Implement the Zilsd extension (load/store pair), enabled by EXTENSION_ZILSD
• Implement the Zclsd extension (compressed load/store pair), enabled by EXTENSION_ZCLSD
• Implement the Zbkx extension (crossbar permutation), enabled by EXTENSION_ZBKX
• Implement TOR region support for PMP, enabled by PMP_MATCH_TOR
  • NAPOT/NA4 matching is now optional, enabled by PMP_MATCH_NAPOT
• Implement interrupt, exception and instruction count trigger in the Trigger Module
  • These triggers are present whenever debug support is enabled by DEBUG_SUPPORT
• Implement the RV32E base extension, enabled by EXTENSION_E
• Implement new custom extension, Xh3misa, for detecting processor ISA support at finer granularity than the standard misa register

Fixed errata:

• Fix fence.i only ordering against the address phase of a preceding store (a multi-manager AHB fabric may reorder address phases, so order against the data phase instead)
• Fix local monitor flag being cleared by trap entry as well as trap exit (only xRET should clear it)
  • This behaviour continues to not affect entry/exit to Debug Mode, so LR/SC sequences can be single-stepped
• Fix the Debug Module PROGBUF1 register being writable when an abstract command is executing, and not setting abstracts.cmderr to busy when written.
• Fix spurious dependency of CSR instructions on rs2, causing read-after-write stall

PPA optimisations:

• Move breakpoint PC comparator from stage 2 to stage 1
• Move PMP X permission lookup from stage 2 to stage 1
• Simplify PMP X permission lookup by looking up naturally-aligned fetches instead of both halfwords of a potentially unaligned instruction
• Move compressed instruction expansion from stage 2 to stage 1
• Pre-decode rs1/rs2 bypass controls in stage 1
• Restore register on op_b input of hazard3_muldiv_seq for better routing locality

General improvements:

• Relax PMP X permission checking to allow instructions to straddle two PMP regions which both have the necessary permissions
• RTL is now lint-clean with Verilator v5.036
• Add Verilator testbench, command-line-compatible with existing CXXRTL testbench
• Update to latest version of riscv-arch-test

Other changes:

• Writes to CSRs which affect instruction fetch now cost three cycles plus an additional cycle if the following instruction is unaligned 32-bit
  • Specifically this affects pmpaddr*, pmpcfg*, tcontrol, tdata1 and tdata2
  • These CSR writes now require an instruction fetch flush to enforce the necessary orderings
  • All other CSRs remain single-cycle write

v1.0.2

This point release fixes one issue from the previous release, v1.0.1:

• Coding style change for Verilator compatibility: reported in issue #21

This issue affects multiple versions of Verilator, so has been released directly to stable as a point fix.

v1.0.1

This point release fixes one erratum from the previous release, v1.0:

• Abstract access commands initiated via abstractauto access the wrong core GPR: reported in #20, fixed by cb700f3.

This erratum mainly affects debugger memory downloads without the use of System Bus Access. It is not present on the Hazard3 version used on RP2350.

This release also contains some minor documentation updates since v1.0, clarifying PMP region types supported by Hazard3.

v1.0

This is the first stable release of Hazard3. It fixes the following errata from the v1.0-rc2 release candidate:

• PMPCFG fields R and X are transposed: fixed by 7d37029
• mstatus.mie is not ignored in U-mode: fixed by a84742a

It adds one new hardware feature:

• Set the misa.b bit when ZbaZbbZbs are all present (B was recently ratified as this combination)

It contains the following improvements:

• Fix compatibility issues with Verilator related to parameter-controlled widths of parameters
• General RTL cleanup: now lint-clean with Verilator
• Updates to documentation including documenting all top-level ports of hazard3_cpu_1port and hazard3_cpu_2port
• Updates to Readme.md instructions to work with the latest versions of tools
• Updates to software Makefiles etc to all work with the GCC 14 configuration recommended in Readme.md
• Remove global environment variables like $PROJ_ROOT which caused issues like #8
• Minor PPA improvements due to streamlining of Zcmp decode, and decoding bypass controls at the end of stage 1
• Improvements to the rvcpp simulator to cover more Hazard3 implementation-defined behaviour (and all of its ISA support)
• Fix fence.i being promoted to a trap in Debug mode (this was a deliberate choice at the time but is confusing/inconsistent; fixed by 96e0e66)

This release has one known erratum:

• Abstract access commands initiated via abstractauto access the wrong core GPR: reported in #20, fixed by cb700f3.

The attached documentation PDF is built from this tag. It contains one known documentation erratum:

• The encoding tables for h3.bextm and h3.bextmi are incorrect as they duplicate bits 1:0; discussed in #17, fixed in f14432c

v1.0-rc2

Besides some new tests, script updates and maintenance, this release fixes the following three errata from the previous release:

• Unpredictable behaviour when Zcmp cm.popret is interrupted during the PC-setting uop step: fixed by 2f6e983
• SBA accesses fail to make progress when the processor clock is gated during sleep: fixed by c11581e
• New SBA reads can still be initiated whilst sbcs.sberror or sbcs.sbbusyerror are set, causing spurious downstream reads and address increments: fixed by af08c0b

This release candidate has the following known errata:

• PMPCFG fields R and X are transposed: fixed by 7d37029
• mstatus.mie is not ignored in U-mode: fixed by a84742a

v1.0-rc1

This release candidate has the following known errata, fixed in later releases:

• Unpredictable behaviour when Zcmp cm.popret is interrupted during the PC-setting uop step: fixed by 2f6e983
• SBA accesses fail to make progress when the processor clock is gated during sleep: fixed by c11581e
• New SBA reads can still be initiated whilst sbcs.sberror or sbcs.sbbusyerror are set, causing spurious downstream reads and address increments: fixed by af08c0b
• PMPCFG fields R and X are transposed: fixed by 7d37029
• mstatus.mie is not ignored in U-mode: fixed by a84742a