v1.1-rc1

Incompatible changes:

• The MHARTID_VAL parameter has been removed, and replaced with the mhartid_val port
• The MIMPID_VAL parameter has been removed
• The mimpid CSR has been redefined to contain the hardcoded Hazard3 release version

New signals:

• fence_i_vld, fence_d_vld and fence_rdy allow external hardware to enforce memory orderings or trigger cache flushes
• mhartid_val allows a dynamic mhartid CSR value
• eco_version allows modifying part of the processor's reported version number in mimpid

New features:

• Implement the Zilsd extension (load/store pair), enabled by EXTENSION_ZILSD
• Implement the Zclsd extension (compressed load/store pair), enabled by EXTENSION_ZCLSD
• Implement the Zbkx extension (crossbar permutation), enabled by EXTENSION_ZBKX
• Implement TOR region support for PMP, enabled by PMP_MATCH_TOR
  • NAPOT/NA4 matching is now optional, enabled by PMP_MATCH_NAPOT
• Implement interrupt, exception and instruction count trigger in the Trigger Module
  • These triggers are present whenever debug support is enabled by DEBUG_SUPPORT
• Implement the RV32E base extension, enabled by EXTENSION_E
• Implement new custom extension, Xh3misa, for detecting processor ISA support at finer granularity than the standard misa register

Fixed errata:

• Fix fence.i only ordering against the address phase of a preceding store (a multi-manager AHB fabric may reorder address phases, so order against the data phase instead)
• Fix local monitor flag being cleared by trap entry as well as trap exit (only xRET should clear it)
  • This behaviour continues to not affect entry/exit to Debug Mode, so LR/SC sequences can be single-stepped
• Fix the Debug Module PROGBUF1 register being writable when an abstract command is executing, and not setting abstracts.cmderr to busy when written.
• Fix spurious dependency of CSR instructions on rs2, causing read-after-write stall

PPA optimisations:

• Move breakpoint PC comparator from stage 2 to stage 1
• Move PMP X permission lookup from stage 2 to stage 1
• Simplify PMP X permission lookup by looking up naturally-aligned fetches instead of both halfwords of a potentially unaligned instruction
• Move compressed instruction expansion from stage 2 to stage 1
• Pre-decode rs1/rs2 bypass controls in stage 1
• Restore register on op_b input of hazard3_muldiv_seq for better routing locality

General improvements:

• Relax PMP X permission checking to allow instructions to straddle two PMP regions which both have the necessary permissions
• RTL is now lint-clean with Verilator v5.036
• Add Verilator testbench, command-line-compatible with existing CXXRTL testbench
• Update to latest version of riscv-arch-test

Other changes:

• Writes to CSRs which affect instruction fetch now cost three cycles plus an additional cycle if the following instruction is unaligned 32-bit
  • Specifically this affects pmpaddr*, pmpcfg*, tcontrol, tdata1 and tdata2
  • These CSR writes now require an instruction fetch flush to enforce the necessary orderings
  • All other CSRs remain single-cycle write