[RWRoute] General + SLR crossing optimizations

[eddieh-xlnx]

• General optimizations
  • Cap bias cost to 0.5 * node cost (as described in CRoute paper)
  • Nodes that do not feed-through to sink tile are no longer accessible
• Optimize SLR crossings
  • Only explore crossings in the right direction (towards sink)
  • Perform "lookahead" on nodes that lead to a SLR crossing (rather than push those nodes onto the queue, immediately explore their children) because the SLL node (which gives a big cost reduction) is several nodes deep and can take many unguided pops to finally get to
    • Lookahead is performed on INODE and IMUXes that lead to a SLL, as well as SDQNODE and intra-tile NODE_SINGLEs that lead to those INODEs.
  • Return to pre-[RWRoute] Yet more cleanup #1107 estimates for SLR crossings, whereby nodes that overshoot a Laguna column by <= 2 tiles, on the way to the sink, will be guided to that column so that early crossings can be considered
  • For connection using Laguna registers, project over the SLL to the IMUX leading into/LOGIC_OUTS leading from that SLL

[eddieh-xlnx]

On the FPGA24 Routing Contest:

master @ 4e804c
+--------------------------------+-------+---------------+--------------+
| Benchmark                      | Pass  | RWRoute (sec) | Nodes Popped |
+--------------------------------+-------+---------------+--------------+
| logicnets_jscl_rwroute         | False |         43.70 |     54493698 |
| boom_med_pb_rwroute            | False |        264.78 |    272740956 |
| vtr_mcml_rwroute               | False |        254.03 |    339041410 |
| rosetta_fd_rwroute             | False |        157.40 |    191115169 |
| corundum_25g_rwroute           | False |        281.94 |    278838734 |
| finn_radioml_rwroute           | False |         87.57 |    115746783 |
| vtr_lu64peeng_rwroute          | False |        202.08 |    215449340 |
| corescore_500_rwroute          | False |        137.62 |    122093928 |
| corescore_500_pb_rwroute       | False |        297.14 |    239000597 |
| mlcad_d181_lefttwo3rds_rwroute | False |       2124.62 |   1730785359 |
| koios_dla_like_large_rwroute   | False |        308.15 |    299273289 |
| boom_soc_rwroute               | False |       1163.78 |   1503721309 |
| ispd16_example2_rwroute        | False |        478.08 |    514270796 |
+--------------------------------+-------+---------------+--------------+

versus

This PR @ d95d71e
+--------------------------------+------+---------------+--------------+
| Benchmark                      | Pass | RWRoute (sec) | Nodes Popped |
+--------------------------------+------+---------------+--------------+
| logicnets_jscl_rwroute         | True |         38.16 |     54548378 |
| boom_med_pb_rwroute            | True |        237.48 |    264311422 |
| vtr_mcml_rwroute               | True |        277.06 |    315542555 |
| rosetta_fd_rwroute             | True |        163.48 |    191021706 |
| corundum_25g_rwroute           | True |        265.02 |    269192989 |
| finn_radioml_rwroute           | True |         91.93 |    116197927 |
| vtr_lu64peeng_rwroute          | True |        182.48 |    226684481 |
| corescore_500_rwroute          | True |        137.03 |    121346442 |
| corescore_500_pb_rwroute       | True |        297.98 |    238072644 |
| mlcad_d181_lefttwo3rds_rwroute | True |       1820.81 |   1537074340 |
| koios_dla_like_large_rwroute   | True |        301.73 |    301754940 |
| boom_soc_rwroute               | True |       1155.66 |   1423703585 |
| ispd16_example2_rwroute        | True |        460.58 |    521990720 |
+--------------------------------+------+---------------+--------------+

On average, -6% runtime and -5% nodes popped.