Add ability to constrain flop harness to specific side of PBlock #1318
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…k to improve routability. Also unroute top-level I/O nets that exit the pblock. Signed-off-by: Andrew Butt <[email protected]>
This was referenced Nov 7, 2025
Signed-off-by: Andrew Butt <[email protected]>
…explorer-side-map
clavin-xlnx
reviewed
Nov 11, 2025
| } | ||
| Site shiftedSite = shiftSiteToSide(design.getDevice(), start, keepOut, side); | ||
| if (port.isBus()) { | ||
| for (int i : port.getBitBlastedIndicies()) { |
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This is a lot of duplicated code. I realize this is partly due to the nature of bussed vs. single bit ports. One way to work around this is to use this pattern:
for (int i : (port.isBus() ? port.getBitBlastedIndicies() : new int[] { 0 })) {
EDIFPortInst portInst = port.getInternalPortInstNameFromIndex(i));A better solution might be to modify EDIFPort.getBitBlastedIndicies() so that for the single bit case it returns a static new int[] { 0 }.
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We decided that getBitBlastedIndicies should be updated to return { 0 } when called on a non-bused port. I will refactor further once this change has been made.
Signed-off-by: Andrew Butt <[email protected]>
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To ensure routability of ArrayBuilder designs, it is important that there is a routing path from a precompiled module in the direction of the input of the next precompiled module. A side map is provided to PerformanceExplorer which specifies which side of the pblock a given top-level I/O should have its flop placed on. Also unroutes top-level I/O nets that exit the pblock to prevent node overlaps between blocks placed near each other in the array.