RapidWright 2025.1.3-beta Release

Release Notes:

• [RWRoute] Versal fixes for clocking, static nets and general routing (#1280)
• [DesignTools] createCeClkOfRoutethruFFToVCC() to handle AND2B1L/OR2L (#1286)
• [TestBELPin] Test that BELPin.getConnectedSitePin() thru IMRs (#1285)
• Adds RW_COPY_EDNS_ON_DCP_WRITE and adds helper to extract EDNs (#1288)
• Move Site.getIntTile() -> DeviceTools.getIntTile() and fix for Versal (#1287)
• Cannot close the zip file (refactor?) (#1289)
• Cleanup gradle 9 warnings and Java linting warnings for Java 17 (#1277)
• [DesignTools] Handles VCC/GND connections properly in populateBlackBox() (#1278)
• rc2 and tests for removing alternate SPIs (#1276)
• [TimingGraph] Improving Report Timing Example; add some APIs (#1273)
• Propagates EDN files when loading RapidWright-generated DCPs
• [BELPin] getConnectedSitePin() to punch thru IMRs
• Site.getIntTile() to call DeviceTools.getIntTile(Site)
• Fix SitePinInst removal for alternate pins
• Address unplaced modules when getting BELPins

API Additions:

Note: The 2025.1.2 release was scrapped. The rapidwright-api-lib jar got corrupted on Maven Central so this release version
had to be abandoned, was released 2025.1.3 in its place.

RapidWright 2025.1.1-beta Release

Release Notes:

• Unisim Primitive Mappings Updates for Versal (#1271)
• [ECOTools.connectNet()] Fixes static net connection and no source issues (#1270)
• [RWRoute] Add support for SLL tile types (#1269)
• Test and fixes for Versal site routing support (#1267)
• Netlist Comparator Inst and Property Tracking (#1260)
• Fix an issue on calculateUtilization function for Versal devices. (#1264)
• Add support for shared sink SitePinInsts in LUTInputConeOpt (#1262)
• Update Versal Unisims (#1261)
• EDIFNetlistComparator Test (#1263)
• Minor Changes to PBlock and LUT eval fixes (#1257)
• Versal LUT Input Routing Fixes and Test (#1254)
• [EDIFTools] Fix connectPortInstsThruHier when finding source pin (#1258)
• [RWRoute] Cleanup RWRoute.isAccessibleSink() (#1256)
• [EDIFTools] Add support for connecting logical nets through both hierarchical directions (#1253)
• [RWRoute] General + SLR crossing optimizations (#1232)
• [ReportRouteStatus] Do not count nets with no pins (#1248)
• [EDIFNetlist] Create a wrapper EDIFCell constructor (#1238)
• Test that Versal site pins are acquired correctly (#1247)
• Inline Flop Insertion/Removal Tool (#1242)
• Reset diffCount when compareNetlists is ran (#1251)
• Continue if cell is null (#1250)

API Additions:

• com.xilinx.rapidwright.design.Design "public static Map<SiteTypeEnum, Set> getCompatiblePlacements(Device device, Unisim u)"
• com.xilinx.rapidwright.design.Design "public static Map<SiteTypeEnum, Set> getCompatiblePlacements(String deviceName, Unisim u)"
• com.xilinx.rapidwright.device.BEL "public boolean isAnyIMR()"

RapidWright 2025.1.0-beta Release

Release Notes:

• Add methods to access internal DiffMap (#1234)
• [EDIFNetlist] Update library when renaming cells; add API to remove blackbox prop (#1226)
• Fixes to count LOOKAHEAD8 cells in Versal designs (#1230)
• [NetlistBrowser] Fix extra click issue with instances (#1229)
• [Netlist Browser] GUI Widget to browse a loaded netlist (#1225)
• [CopyImplementation] Command-line version of DesignTools.copyImplementation() (#1215)
• [DesignTools.copyImplementation()] Support Versal IMR routethrus (#1224)
• [ECOTools] connectNet() remove static net assertion (#1223)
• [ECOTools] Fix connectNet() for pins that don't need routing (#1222)
• [LUTTools] Properly size LUTCY* primitives (#1221)
• [LUTInputConeOpt] Enable unplaced netlists (#1213)
• [PhysNetlistWriter] Treat bidir BEL pins on PS8 as output (#1214)
• [ECOTools] Augments connectNet() to handle dual-LUT pin usage scenarios (#1209)
• Basic VS Code Settings (#1210)
• LUT Input Cone Optimization (#1205)
• Design Obfuscator - Flattens design and uses hashing to obfuscate names (#1196)
• Regroup Instances -- command line tool (#1201)
• [PartialDFXRouter] Add PartialRouter specialization for DFX designs (#1204)
• [RWRoute] Connection.setAllTargets() to always set primary sink (#1206)
• [ECOPlacementHelper] Fix NPE for getUnusedFlop() (#1207)
• [Actions] Remove gradle/wrapper-validation-action (#1208)
• [RWRoute] Minor cleanup (#1203)
• [Design.createModuleInst()] Handles black boxes by renaming prior to Design.addModule()
• Fixes gap routing issue
• Improves NOC traffic parsing file

API Additions:

• (None)

RapidWright 2024.2.3-beta Release

Release Notes:

• Add testcase for #780 (Design.routeSites()) (#1191)
• Post-route fanout optimization (#1178)
• Updating Gradle to support Java 21 (#1197)
• [RouterHelper] getPIPsFromNodes() to propagate locked state (#1189)
• Modify API to enable netlist regrouping on non-implemented netlists (#1199)
• [EDIFTools] Enables downward hierarchy traversal when connecting logical nets (#1180)
• [RouterHelper] Invert logical connection of LUT input pins (#1176)
• [Utils] isClocking() to recognize all {CMT,CLK,RCLK}_* tile types (#1190)
• [ModuleInst] Connect port to GND or VCC (#1182)
• [MakeBlackBox] Fixes for unplaced designs (#1164)
• [EDIFTools] uniqueifyNetlist() to use hier paths to cells (#1181)
• LUT1 Insertion Tool (for DFX/Abstract Shell designs) (#1174)
• Add option for DFX bitstreams (#1179)
• [DesignTools] updatePinIsRouted() to handle routing loops (#1185)
• [EDIFTools] UniqueifyNetlist() to reset parent net map (#1175)
• [DesignTools] getAllRoutedSitePinsFromPhysicalPin() fix (#1173)
• [NetTools] Recognize BUFGCE_HDIO as a clock src site (#1172)
• Adds option to preserve routing upon populateBlackBox() (#1171)
• [ReportRouteStatusResult] Parse # of fixed/explicit gap net (#1166)
• [Actions] Update test-rapidwright-wrapper to setup-java@v4 (#1167)
• [ECOTools] Refactor cell from one hier to another (#1159)
• modify affiliation, revise input argv, and rename class name (#1162)
• [CodeGenerator] Creates Java Code to Construct a Test Design With a Single Example SiteInst (#1160)
• Net.connect() Improvements - Better support for hierarchy and connecting to GND/VCC
• Fixes two issues related to reproducing routing in DCPs
• Fix roundtrip DCP routing issue related to partially routed clock net with gap routing

API Additions:

• com.xilinx.rapidwright.design.Design "public List getPartitionPins(Net net)"
• com.xilinx.rapidwright.design.Design "public Net getNetFromPartitionPin(PartitionPin p)"

RapidWright 2024.2.2-beta Release

Release Notes:

• [DesignTools] Fix routethru corner case in fullyUnplaceCellHelper() (#1157)
• Add option to uniquify copied cells (#1156)
• [DesignTools] Ensure cell pin has a logical connection before attempting to unroute it (#1154)
• [DesignTools] Unroutes both CLK pins on a BRAM when requested (#1151)
• [EDIF] Fix Export of Single Bit Busses (#1147)
• Fixes to enable BlockStitcher to run (#1134)
• Enables batching of SitePinInst removals during MakeBlackBox (#1142)
• Routing Heat Map Example (#1145)
• When adding Modules to Designs, make EDIF cell names unique if name collides

API Additions:

• com.xilinx.rapidwright.design.Design "public boolean removeSiteInst(SiteInst instance, boolean keepSitePinRouting,
• com.xilinx.rapidwright.design.Design "public Map<SiteTypeEnum, Set> getCompatiblePlacements(Unisim u)"
• com.xilinx.rapidwright.design.Design "public static Map<SiteTypeEnum, Set> getCompatiblePlacements(FamilyType family, Unisim u)"

RapidWright 2024.2.1-beta Release

Release Notes:

• Adds an Override Flag for Advanced Flow Settings in Designs (#1135)
• Test for SiteInst.isEmpty() (#1128)
• Tests for Versal BEL flags and site unrouting (#1125)
• [LUTTools] Versal pin swapping fixes (#1130)
• [DesignTools] foreachConnectedBELPin() to walk through Versal IMRs (#1129)
• [DesignTools] updatePinsIsRouted() to return num unrouted sinks (#1131)
• [TestDesign] Add testPlaceCellPinMappings() (#1122)
• [RWRoute] Small cleanup; enable CUFR by default (#1126)
• RWRoute preprocessing fixes (#1119)
• Enables setting Advanced Flow Flags for Designs
• Corrects and Adds BEL flags; fixes unroute site net for Versal
• [Cell] Fixes to P2L and L2P

API Additions:

• com.xilinx.rapidwright.design.Cell "public void fixCell(boolean isFixed)"
• com.xilinx.rapidwright.design.Cell "public boolean isCellFixed()"
• com.xilinx.rapidwright.design.Design "public boolean isAdvancedFlow()"
• com.xilinx.rapidwright.design.Design "public void setAdvancedFlow(boolean val)"
• com.xilinx.rapidwright.design.SiteInst "public boolean isEmpty()"
• com.xilinx.rapidwright.device.BEL "public boolean isCEIMR()"
• com.xilinx.rapidwright.device.BEL "public boolean isSliceIMRClkMod()"

RapidWright 2024.2.0-beta Release

Release Notes:

• The memory usage improvements in this release reduce a routed DCP footprint by 10-20%
• Remove reliance on gap routing test (#1117)
• [ModuleInst] Fix placement behavior when requesting no overlaps (#1108)
• [RWRoute] Clock router for Versal architecture (#1102)
• Various preprocessing fixes for Versal routing (#1115)
• [CUFR] CUFR and PartialCUFR to default to --hus (#1111)
• [TestNet] Improve testSetPinsMultiSrcStatic to track many sources (#1082)
• Changes to support new array-based cell pin mappings (#1101)
• Update tests to reflect bug fixes and minor behavior changes (#1110)
• [RWRoute] Yet more cleanup (#1107)
• [RWRoute] Preserve nodes of Laguna sinks (#1104)
• [GlobalSignalRouting] routeStaticNets() to take a list of static pins (#1105)
• [RWRoute] Fix typo -- not an exclusive sink (#1106)
• [RWRoute] Versal optimizations (#1093)
• [RWRoute] RouteNode.setType() to accept any locals (#1103)
• [RWRoute] Further divide LOCAL nodes into EAST/WEST for UltraScale(+) (#1098)
• [Utils] isClocking() to include TileTypeEnum.CMT_L (#1100)
• TileGroup and DeviceBrowser Improvements (#1094)
• [RWRoute] Divide nodes into LOCAL and NON_LOCAL (#1095)
• Update actions and do not limit to 5G RAM (#1092)
• [HandPlacer] Cleanup snapping code in hand placer (#1091)
• [LUTTools] Add zero padding to LUT INIT strings (#1090)
• [NetTools] Add getNodeTrees() method and NodeTree class (#1089)
• [YosysTools] Add synthXilinx() wrapper for Yosys (#1086)
• [EDIFWriteLegalNameCache] busCollisionRenames to be a ConcurrentHashMap (#1088)
• Add ReportRouteStatus utility (#1087)
• [RWRoute] Signal router for Versal architecture (#1077)
• [FileTools] Add runCommand(String[] ...) & getExecutablePath(String) (#1085)
• [RouterHelper] findPathBetweenNodes() allow clocking if src/sink is so (#1083)
• [RouterHelper] projectOutputPinToINTNode() to breadth-first-search (#1081)
• [RouterHelper] projectInputPinToINTNode() to return solitary node (#1080)
• [RouterHelper] findPathBetweenNodes() to ignore clocking tiles (#1079)
• [RouterHelper] invertPossibleGndPinsToVccPins() to support Versal LUTs (#1078)
• [DesignTools] Fix createCeSrRstPinsToVCC() for US BRAMs (#1075)
• [DesignTools] Add LDCE/LDPE to types that need VCC (#1076)
• [NetTools] Add NetTools.isGlobalClock() (#1057)
• Static router for Versal architecture (#1073)
• [EDIFNetlist] getPhysicalPins() to call getPhysical{Gnd,Vcc}Pins() (#1074)
• Fix Null SLR References in Tiles in xcvp1902
• Add Implements Serializable to All RapidWright Classes
• [SiteInst] Improve memory usage of site routing using array instead of maps
• [Cell] Changes pin mappings from a map to an array to improve memory usage
• [BEL] Deprecate isSRIMR() in favour of more general isIMR()
• [Tile] Add getMaxUniqueAddress()
• [Net] Add support for multiple output sources

API Additions:

• com.xilinx.rapidwright.design.Cell "public Pair<BELPin, String> getFirstPhysicalPinMapping()"
• com.xilinx.rapidwright.design.Cell "public int getUsedPhysicalPinsCount()"
• com.xilinx.rapidwright.design.Cell "public Set getUsedPhysicalPins()"
• com.xilinx.rapidwright.design.Cell "public String[] getPhysicalPinMappings()"
• com.xilinx.rapidwright.design.Cell "public boolean usesPhysicalPin(String physicalPinName)"
• com.xilinx.rapidwright.design.Design "public boolean placeCell(Cell c, Site site, BEL bel, String[] physPinMappings)"
• com.xilinx.rapidwright.design.Net "public List getAlternateSources()"
• com.xilinx.rapidwright.device.BEL "public boolean isIMR()"
• com.xilinx.rapidwright.device.Tile "public int getMaxUniqueAddress()"

RapidWright 2024.1.3-beta Release

Release Notes:

• [RWRoute] Further cleanup (#1070)
• [PhysNetlistReader] Call SiteInst.setDesign() even for STATIC_SOURCEs (#1071)
• [GlobalSignalRouting] Fix VCC routing for UltraScale (#1068)
• [RWRoute] Cleanup static router and RouterHelper (#1059)
• [PartialRouter] Disable ripup in global/static routing (#1067)
• [TestDesign] Add test for net ordering of >= 2022.1 DCPs (#1054)
• [TestBEL] Add testDIFFsAreNotFF() (#1062)
• Test for Design.retargetPart() (#1061)
• [EDIF] Fixes rare bus renaming collision (#1065)
• [RWRoute] Always clear prev pointer of unpreserved RouteNode-s (#1056)
• [LaunchTestsOnLsf] Invoke java with assertions enabled (#1066)
• [LaunchTestsOnLsf] Invoke java with assertions enabled (#1063)
• Fix testRouteStaticNet() to avoid site pins, and fix golden values (#1064)
• [GitHub Actions] Migrate to upload-artifact@v4 (#1058)
• Add recursive partitioning ternary tree (RPTT) (#1055)
• Add support for vu19p tiles in bitstream
• [Design] createModuleInst() to not create duplicate STATIC_SOURCE-s
• Removes all instances of enum.hashCode()
• [Node] equals() to use instanceof for subclass-awareness
• Retarget & relocate an existing design to a new part and location
• Fixes issue related to non-deterministic Net order upon multi-threaded DCP load
• Fix BEL.isFF() based on BELTypes
• Fix missing Design.getSeries()

API Additions:

• com.xilinx.rapidwright.design.Design "public boolean retargetPart(Part targetPart, int tileXOffset, int tileYOffset)"

RapidWright 2024.1.2-beta Release

Release Notes:

• Creating a standalone entry point to relocate DCPs (#1047)
• [Interchange] Reorders tile types and tiles to follow their Vivado index (#1039)
• [DesignTools] Conform to Vivado RST pin inversion site routing configuration (#1053)
• Fix for design merging, including designs with encrypted cells (#1035)
• Filters out comments in XDC while parsing clk constraints (#1037)
• Assign an empty list when path finding for direct connections fails (#1052)
• Make LogicalNetlistToEdif not expand macros by default (#1051)
• [Interchange] Fixes to support Versal designs via Interchange (#1040)
• EDIF cleanup preventing singleton cells/libraries from attaching to user designs (#1050)
• [RWRoute] Refactoring/cleanup/preparation for multi-threading (#1046)
• Add Hybrid Updating Strategy (HUS) (#1043)
• [TestSiteInst] Add test for unrouting through FF routethru cells (#1041)
• [TestPIP] Test PIP constructor for reversed wires (#1045)
• [RWRoute] Preserve primary source nodes on connections (#1038)
• Small Interchange/PhysNetlistReader/VivadoTools improvements (#1042)
• [UnisimManager] Use EDIFLibraryBuiltin for primitive/macro libs
• Avoids NPE when site routing BRAMs
• Fix isCarry() for Versal devices
• Resolves PIP constructor issue for reversed PIPs
• [SiteInst] unrouteIntraSiteNet() to handle FF routethru cells

API Additions:

• com.xilinx.rapidwright.design.Design "public Series getSeries()"
• com.xilinx.rapidwright.design.SiteInst "public SitePIP getUsedSitePIP(BEL bel)"

RapidWright 2024.1.1-beta Release

Release Notes:

• [VivadoTools] Source *_load.tcl from same dir as DCP (#1032)
• Test that PIP.isReversed() is correct (#1024)
• Add TestSite.testGetIntTile() (#1022)
• [EDIFTools] writeTclLoadScriptForPartialEncryptedDesigns abspath (#1029)
• Adding HDIOB types (#1028)
• Test for site routing from raw placed design (#1000)
• [RWRoute] Do not NPE on encrypted netlists (#1025)
• [RWRoute] Do not assume Y = 0 has Laguna tiles, since it could be HBM device (#1026)
• Adds UNKWN state for LSFJobs (#1027)
• Adding legacy support for u280 (#1021)
• Remove flawed loop intended to for encrypted cell removal (#1023)
• [DesignTools.makeBlackBox()] Fixes an issue of removing CARRY blocks fed by routethrus (#1009)
• Fix null netlist pointer on expanded macro children (#1008)
• [Interchange] Device Resources Verifier Fixes (#1014)
• Fix ConcurrentModificationError (#1015)
• [EDIFTools] Adding method to create a flat netlist from a hierarchical one (#1006)
• Adding HBM ComponentTypes (#1007)
• Test for wire/node mismatch reported in #983 (#1005)
• 3.6% memory reduction usage for large placed designs (de-duplication of cell pin strings)
• Add missing pin entry for BUFG_GT when tracking INT tile connections
• Fixes rare DCP write issue with stubbed bi-directional PIPs (more common on DFX designs)
• Fix for reversed flag on PIPs
• Addresses issue with Net.getBufferDelay() by checking for null wire names
• Fixes two site routing issues