Add support for 16-bit and 32-bit VInserts in PreLegalizerCombiner

Xilinx · Nov 4, 2024 · 894850d · 894850d
1 parent 4c793d4
commit 894850d
Show file tree

Hide file tree

Showing 2 changed files with 397 additions and 5 deletions.
diff --git a/llvm/lib/Target/AIE/AIE2PreLegalizerCombiner.cpp b/llvm/lib/Target/AIE/AIE2PreLegalizerCombiner.cpp
@@ -191,9 +191,19 @@ std::map<unsigned, Register>
 AIE2PreLegalizerCombinerImpl::getVectorInsertIndices(
     MachineInstr *CurMI, unsigned SclSrcBits, MachineRegisterInfo &MRI) const {
   std::map<unsigned, Register> RegMap;
-  auto Is8BitVInsert = [](const MachineInstr *MI) {
-    return isa<GIntrinsic>(MI) && cast<GIntrinsic>(*MI).getIntrinsicID() ==
-                                      Intrinsic::aie2_vinsert8_I512;
+  auto IsVInsert = [](const MachineInstr *MI, unsigned SclSrcBits) {
+    if (!isa<GIntrinsic>(MI))
+      return false;
+    switch (cast<GIntrinsic>(*MI).getIntrinsicID()) {
+    case Intrinsic::aie2_vinsert8_I512:
+      return SclSrcBits == 8;
+    case Intrinsic::aie2_vinsert16_I512:
+      return SclSrcBits == 16;
+    case Intrinsic::aie2_vinsert32_I512:
+      return SclSrcBits == 32;
+    default:
+      return false;
+    }
   };
   auto IsSet = [](const MachineInstr *MI) {
     return isa<GIntrinsic>(MI) && (cast<GIntrinsic>(*MI).getIntrinsicID() ==
@@ -202,7 +212,7 @@ AIE2PreLegalizerCombinerImpl::getVectorInsertIndices(
                                        Intrinsic::aie2_set_I512_I256);
   };
 
-  while (Is8BitVInsert(CurMI)) {
+  while (IsVInsert(CurMI, SclSrcBits)) {
     // In this case of G_INTRINSIC operand 1 is target intrinsic
     const Register SrcReg = CurMI->getOperand(2).getReg();
     const Register IdxReg = CurMI->getOperand(3).getReg();
@@ -264,7 +274,11 @@ bool AIE2PreLegalizerCombinerImpl::tryToCombineVectorInserts(
   MIRBuilder.buildBuildVectorTrunc(DstRegTrunc, Regs);
   MIRBuilder.buildInstr(AIE2::G_AIE_PAD_VECTOR_UNDEF, {DstRegPad},
                         {DstRegTrunc});
-  MIRBuilder.buildBitcast(DstReg, DstRegPad);
+  // Avoid bitcast if types match, use copy instead
+  if (MRI.getType(DstRegPad) == MRI.getType(DstReg))
+    MIRBuilder.buildCopy(DstReg, DstRegPad);
+  else
+    MIRBuilder.buildBitcast(DstReg, DstRegPad);
 
   MI.eraseFromParent();
   return true;
@@ -286,6 +300,12 @@ bool AIE2PreLegalizerCombinerImpl::tryToCombineIntrinsic(
   case Intrinsic::aie2_vinsert8_I512: {
     return tryToCombineVectorInserts(MI, 8);
   }
+  case Intrinsic::aie2_vinsert16_I512: {
+    return tryToCombineVectorInserts(MI, 16);
+  }
+  case Intrinsic::aie2_vinsert32_I512: {
+    return tryToCombineVectorInserts(MI, 32);
+  }
   default:
     break;
   }