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[AIE2] Simplify sequence of VInserts to G_BUILD_VECTOR #187

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merged 3 commits into from
Oct 29, 2024

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abhinay-anubola
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@abhinay-anubola abhinay-anubola commented Sep 17, 2024

Simplify sequence of VInserts by legalizing G_BUILD_VECTOR_TRUNC and combining VInsert sequence in PreLegalizerCombiner into G_BUILD_VECTOR_TRUNC

@abhinay-anubola abhinay-anubola force-pushed the sanubola.simplify.VINSERT.sequence branch 3 times, most recently from 1aa3088 to 5b7e112 Compare September 19, 2024 08:54
@abhinay-anubola abhinay-anubola force-pushed the sanubola.simplify.VINSERT.sequence branch 6 times, most recently from 6395c61 to 46de687 Compare October 4, 2024 06:30
@abhinay-anubola abhinay-anubola marked this pull request as ready for review October 4, 2024 06:31
@abhinay-anubola abhinay-anubola force-pushed the sanubola.simplify.VINSERT.sequence branch from 46de687 to 34ab0eb Compare October 4, 2024 12:25
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I ran QoR with the updated changes, but the results remain unchanged compared to the previous run.

@abhinay-anubola abhinay-anubola force-pushed the sanubola.simplify.VINSERT.sequence branch from bfbb569 to 3cf078b Compare October 21, 2024 14:39
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gbossu commented Oct 22, 2024

LGTM, I just think it is important to fix #187 (comment)

@abhinay-anubola abhinay-anubola force-pushed the sanubola.simplify.VINSERT.sequence branch from 3cf078b to 2f616e5 Compare October 22, 2024 09:41
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gbossu commented Oct 22, 2024

I looked at QoR and this seems to cause regressions more than improvements, I'd like to understand them before merging

@abhinay-anubola abhinay-anubola force-pushed the sanubola.simplify.VINSERT.sequence branch 2 times, most recently from df22faa to 7b6fdc3 Compare October 24, 2024 08:53
Register Dst = MRI.createGenericVirtualRegister(VecTy);

if (DstVecSize == 512 && Operand == OperandBegin + 1)
if (DstVecSize == 512 && Operand == OperandBegin) {
Dst = DstReg;
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nit: we've created an unused virtual register.

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Is this about the register Dst, we have used later.

const Register ExtOpIdxReg = ExtOp->getOperand(3).getReg();
auto SetOpCst = getIConstantVRegValWithLookThrough(SetOpIdxReg, MRI);
auto ExtOpCst = getIConstantVRegValWithLookThrough(ExtOpIdxReg, MRI);
if (SetOpIdxReg != ExtOpIdxReg &&
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@martien-de-jong martien-de-jong Oct 24, 2024

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nit: if they are the same, we only need one getIConstantVRegValWithLookThrough and if we don't have SetOpCst, we don't need to find ExtOpCst.

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In that case we will end up having two if blocks.

@abhinay-anubola abhinay-anubola force-pushed the sanubola.simplify.VINSERT.sequence branch from 7b6fdc3 to a778ef1 Compare October 25, 2024 07:51

// Combining Set and Extract to fetch next VInsert
if (IsSet(CurMI) && tryToCombineSetExtract(*CurMI))
CurMI = getDefIgnoringCopies(SrcReg, MRI);
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Isn't tryToCombineSetExtract potentially deleting CurMI? Is it always safe to call CurMI = getDefIgnoringCopies(SrcReg, MRI);?

Regs.push_back(It->second);
}
Register DstRegTrunc = MRI.createGenericVirtualRegister(
LLT::fixed_vector(DstRegLen, SclSrcBits));
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Could we re-use the type from MI.getOperand(0) instead of trying to reconstruct it with LLT::fixed_vector(DstRegLen, SclSrcBits)?

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@abhinay-anubola abhinay-anubola Oct 28, 2024

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We can't do that, as they both are not same. In a case <16 x s32> is type of MI.getOperand(0) and we need <16 x s8> for buildBuildVectorTrunc

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Why is it like this actually, do our VINSERT.S8 intrinsics take a <16 x s32> type?

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yes, they take <16 x s32> type

@abhinay-anubola abhinay-anubola force-pushed the sanubola.simplify.VINSERT.sequence branch from a778ef1 to f0efd5b Compare October 29, 2024 09:59
@abhinay-anubola abhinay-anubola force-pushed the sanubola.simplify.VINSERT.sequence branch from f0efd5b to ecd3fd7 Compare October 29, 2024 11:11
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LGTM, nice work :)

@abhinay-anubola abhinay-anubola merged commit 4c793d4 into aie-public Oct 29, 2024
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@abhinay-anubola abhinay-anubola deleted the sanubola.simplify.VINSERT.sequence branch October 29, 2024 14:02
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4 participants