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[AIE] Block widening register coalescing inside innerloop #406

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Merged
niwinanto merged 2 commits into from
Apr 2, 2025
Merged

[AIE] Block widening register coalescing inside innerloop #406

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8d6b4f7
[AIE] Block widening register coalescing inside innerloop
niwinanto Mar 26, 2025
1f27c64
[NFC] Remove shouldCoalesce from aie base since we want to keep aie2 …
niwinanto Apr 1, 2025
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9 changes: 2 additions & 7 deletions llvm/lib/Target/AIE/AIEBaseRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18,11 +18,8 @@
#include "Utils/AIELoopUtils.h"
#include "llvm/CodeGen/LiveIntervals.h"

namespace llvm {
static cl::opt<bool> EnableCoalescingForWideCopy(
"aie-enable-widen-copy-coalescing",
cl::desc("Enable register coalescing for widening Copy"), cl::init(false),
cl::Hidden);
using namespace llvm;
extern cl::opt<bool> EnableCoalescingForWideCopy;

bool AIEBaseRegisterInfo::shouldCoalesce(
MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
Expand Down Expand Up @@ -57,5 +54,3 @@ bool AIEBaseRegisterInfo::shouldCoalesce(
return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg,
NewRC, LIS);
}

} // namespace llvm
38 changes: 38 additions & 0 deletions llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.cpp
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Expand Up @@ -17,6 +17,8 @@
#include "AIE2PRegisterBankInfo.h"
#include "AIE2PSubtarget.h"
#include "MCTargetDesc/aie2p/AIE2PMCTargetDesc.h"
#include "Utils/AIELoopUtils.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
Expand All @@ -34,6 +36,11 @@ using namespace llvm;

extern cl::opt<bool> SimplifyCRSRRegs;

cl::opt<bool> EnableCoalescingForWideCopy(
"aie-enable-widen-copy-coalescing",
cl::desc("Enable register coalescing for widening Copy"), cl::init(false),
cl::Hidden);

extern llvm::cl::opt<unsigned> ReservedGPRs;

AIE2PRegisterInfo::AIE2PRegisterInfo(unsigned HwMode)
Expand Down Expand Up @@ -603,3 +610,34 @@ bool AIE2PRegisterInfo::isFifoPhysReg(const Register Reg) const {
return Reg.isPhysical() && (AIE2P::FIFO512RegClass.contains(Reg) ||
AIE2P::FIFO1024RegClass.contains(Reg));
}

bool AIE2PRegisterInfo::shouldCoalesce(
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@andcarminati andcarminati Apr 1, 2025

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Maybe it is better to have this code only for AIE2P, as we are not planning to evaluate effects for AIE2 in this moment. Also, we should keep QoR results for AIE2 in a stable state.

MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
const TargetRegisterClass *DstRC, unsigned DstSubReg,
const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {

const unsigned SrcSize = getRegSizeInBits(*SrcRC);
const unsigned DstSize = getRegSizeInBits(*DstRC);
MachineFunction *MF = MI->getMF();
const AIEBaseInstrInfo *TII =
static_cast<const AIEBaseInstrInfo *>(MF->getSubtarget().getInstrInfo());
const unsigned BasicVectorSize = TII->getBasicVecRegSize();
// Should not coalesce if copying from bigger source.
if (!EnableCoalescingForWideCopy && SrcSize < DstSize &&
(SrcSize >= BasicVectorSize || DstSize >= BasicVectorSize)) {
MachineBasicBlock *MBB = MI->getParent();
LiveInterval &LI = LIS.getInterval(MI->getOperand(1).getReg());
const MachineInstr *FirstMI =
LI.empty() ? nullptr : LIS.getInstructionFromIndex(LI.beginIndex());
const MachineInstr *LastMI =
LI.empty() ? nullptr : LIS.getInstructionFromIndex(LI.endIndex());
// Coalescing inside the same basic block found beneficial. So, check that
// the LiveInterval is not just local to MBB.
if (!FirstMI || FirstMI->getParent() != MBB || !LastMI ||
LastMI->getParent() != MBB)
return false;
}

return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg,
NewRC, LIS);
}
5 changes: 5 additions & 0 deletions llvm/lib/Target/AIE/aie2p/AIE2PRegisterInfo.h
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Expand Up @@ -103,6 +103,11 @@ struct AIE2PRegisterInfo : public AIE2PGenRegisterInfo {
bool isFifoPhysReg(const Register Reg) const override;

bool isSimplifiableReservedReg(MCRegister PhysReg) const override;

bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
unsigned SubReg, const TargetRegisterClass *DstRC,
unsigned DstSubReg, const TargetRegisterClass *NewRC,
LiveIntervals &LIS) const override;
};
} // namespace llvm

Expand Down
5 changes: 3 additions & 2 deletions llvm/test/CodeGen/AIE/aie2p/ra/coalesce-widen-copy.mir
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Expand Up @@ -81,13 +81,14 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[MOV_RLC_imm11_pseudo:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 7
; CHECK-NEXT: [[VBCST_16_:%[0-9]+]]:vec512 = VBCST_16 [[MOV_RLC_imm11_pseudo]]
; CHECK-NEXT: undef [[VCONV_fp32_bf16_mv_ups_xbf:%[0-9]+]].sub_1024_acc_lo:acc2048 = VCONV_fp32_bf16_mv_ups_xbf [[VBCST_16_]]
; CHECK-NEXT: [[VCONV_fp32_bf16_mv_ups_xbf:%[0-9]+]]:ecml = VCONV_fp32_bf16_mv_ups_xbf [[VBCST_16_]]
; CHECK-NEXT: [[MOV_RLC_imm11_pseudo1:%[0-9]+]]:er = MOV_RLC_imm11_pseudo 0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead [[VADD_vmac_cm2_add_reg:%[0-9]+]]:acc2048 = VADD_vmac_cm2_add_reg [[VCONV_fp32_bf16_mv_ups_xbf]], [[VCONV_fp32_bf16_mv_ups_xbf]], [[MOV_RLC_imm11_pseudo1]]
; CHECK-NEXT: undef [[COPY:%[0-9]+]].sub_1024_acc_lo:acc2048 = COPY [[VCONV_fp32_bf16_mv_ups_xbf]]
; CHECK-NEXT: dead [[VADD_vmac_cm2_add_reg:%[0-9]+]]:acc2048 = VADD_vmac_cm2_add_reg [[COPY]], [[COPY]], [[MOV_RLC_imm11_pseudo1]]
; CHECK-NEXT: PseudoLoopEnd <mcsymbol .L_LEnd0>, %bb.1
; CHECK-NEXT: PseudoJ_jump_imm %bb.2
; CHECK-NEXT: {{ $}}
Expand Down