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Change WireBundle::Ctrl to WireBundle::TileControl. Decouple WireBund…
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…le and StrmSwPortType (#2010)

Co-authored-by: github-actions[bot] <41898282+github-actions[bot]@users.noreply.github.com>
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@fifield @github-actions
fifield and github-actions[bot] authored Jan 10, 2025
1 parent 1b059e4 commit df46f74
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Showing 15 changed files with 126 additions and 152 deletions.
4 changes: 2 additions & 2 deletions include/aie/Dialect/AIE/IR/AIEAttrs.td
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Original file line number Diff line number Diff line change
Expand Up @@ -49,12 +49,12 @@ def EastWire: I32EnumAttrCase<"East", 6>;
def PLIOWire: I32EnumAttrCase<"PLIO", 7>;
def NOCWire: I32EnumAttrCase<"NOC", 8>;
def TraceWire: I32EnumAttrCase<"Trace", 9>;
def ControlWire: I32EnumAttrCase<"Ctrl", 10>;
def TileControlWire: I32EnumAttrCase<"TileControl", 10>;

def WireBundle: I32EnumAttr<"WireBundle", "Bundle of wires",
[
CoreWire, DMAWire, FIFOWire, SouthWire, WestWire, NorthWire,
EastWire, PLIOWire, NOCWire, TraceWire, ControlWire
EastWire, PLIOWire, NOCWire, TraceWire, TileControlWire
]> {

let cppNamespace = "xilinx::AIE";
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2 changes: 1 addition & 1 deletion include/aie/Targets/AIERT.h
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Original file line number Diff line number Diff line change
Expand Up @@ -77,7 +77,7 @@ static const std::map<xilinx::AIE::WireBundle, StrmSwPortType>
WIRE_BUNDLE_TO_STRM_SW_PORT_TYPE = {
{xilinx::AIE::WireBundle::Core, StrmSwPortType::CORE},
{xilinx::AIE::WireBundle::DMA, StrmSwPortType::DMA},
{xilinx::AIE::WireBundle::Ctrl, StrmSwPortType::CTRL},
{xilinx::AIE::WireBundle::TileControl, StrmSwPortType::CTRL},
{xilinx::AIE::WireBundle::FIFO, StrmSwPortType::FIFO},
{xilinx::AIE::WireBundle::South, StrmSwPortType::SOUTH},
{xilinx::AIE::WireBundle::West, StrmSwPortType::WEST},
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52 changes: 27 additions & 25 deletions lib/Dialect/AIE/IR/AIETargetModel.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -127,7 +127,7 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 0;
return 4;
}
case WireBundle::Ctrl:
case WireBundle::TileControl:
return isShimNOCTile(col, row) ? 1 : 0;
default:
return 0;
Expand Down Expand Up @@ -155,7 +155,7 @@ AIE1TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 0;
return 4;
}
case WireBundle::Ctrl:
case WireBundle::TileControl:
return 1;
default:
return 0;
Expand Down Expand Up @@ -185,7 +185,7 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row,
}
case WireBundle::Trace:
return 1;
case WireBundle::Ctrl:
case WireBundle::TileControl:
return isShimNOCTile(col, row) ? 1 : 0;
default:
return 0;
Expand Down Expand Up @@ -215,7 +215,7 @@ AIE1TargetModel::getNumSourceSwitchboxConnections(int col, int row,
}
case WireBundle::Trace:
return 2;
case WireBundle::Ctrl:
case WireBundle::TileControl:
return 1;
default:
return 0;
Expand Down Expand Up @@ -376,7 +376,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 6;
case WireBundle::South:
return 4;
case WireBundle::Ctrl:
case WireBundle::TileControl:
return 1;
default:
return 0;
Expand All @@ -400,7 +400,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 0;
return 4;
}
case WireBundle::Ctrl:
case WireBundle::TileControl:
return isShimNOCTile(col, row) ? 1 : 0;
default:
return 0;
Expand Down Expand Up @@ -430,7 +430,7 @@ AIE2TargetModel::getNumDestSwitchboxConnections(int col, int row,
return 0;
return 4;
}
case WireBundle::Ctrl:
case WireBundle::TileControl:
return 1;
default:
return 0;
Expand All @@ -449,7 +449,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
case WireBundle::South:
return 6;
case WireBundle::Trace:
case WireBundle::Ctrl:
case WireBundle::TileControl:
return 1;
default:
return 0;
Expand All @@ -475,7 +475,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
}
case WireBundle::Trace:
return 1;
case WireBundle::Ctrl:
case WireBundle::TileControl:
return isShimNOCTile(col, row) ? 1 : 0;
default:
return 0;
Expand Down Expand Up @@ -509,7 +509,7 @@ AIE2TargetModel::getNumSourceSwitchboxConnections(int col, int row,
case WireBundle::Trace:
// Port 0: core trace. Port 1: memory trace.
return 2;
case WireBundle::Ctrl:
case WireBundle::TileControl:
return 1;
default:
return 0;
Expand Down Expand Up @@ -577,18 +577,18 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row,
if (srcBundle == WireBundle::DMA) {
if (dstBundle == WireBundle::DMA)
return srcChan == dstChan;
if (isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::South,
if (isBundleInList(dstBundle, {WireBundle::TileControl, WireBundle::South,
WireBundle::North}))
return true;
}
if (srcBundle == WireBundle::Ctrl) {
if (srcBundle == WireBundle::TileControl) {
if (dstBundle == WireBundle::DMA)
return dstChan == 5;
if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North}))
return true;
}
if (isBundleInList(srcBundle, {WireBundle::South, WireBundle::North})) {
if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::Ctrl}))
if (isBundleInList(dstBundle, {WireBundle::DMA, WireBundle::TileControl}))
return true;
if (isBundleInList(dstBundle, {WireBundle::South, WireBundle::North}))
return srcChan == dstChan;
Expand All @@ -602,18 +602,19 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row,
}
// Shimtile
else if (isShimNOCorPLTile(col, row)) {
if (srcBundle == WireBundle::Ctrl)
return dstBundle != WireBundle::Ctrl;
if (srcBundle == WireBundle::TileControl)
return dstBundle != WireBundle::TileControl;
if (isBundleInList(srcBundle, {WireBundle::FIFO, WireBundle::South}))
return isBundleInList(dstBundle, {WireBundle::Ctrl, WireBundle::FIFO,
WireBundle::South, WireBundle::West,
WireBundle::North, WireBundle::East});
return isBundleInList(dstBundle,
{WireBundle::TileControl, WireBundle::FIFO,
WireBundle::South, WireBundle::West,
WireBundle::North, WireBundle::East});
if (isBundleInList(srcBundle,
{WireBundle::West, WireBundle::North, WireBundle::East}))
return (srcBundle == dstBundle)
? (srcChan == dstChan)
: isBundleInList(dstBundle,
{WireBundle::Ctrl, WireBundle::FIFO,
{WireBundle::TileControl, WireBundle::FIFO,
WireBundle::South, WireBundle::West,
WireBundle::North, WireBundle::East});
if (srcBundle == WireBundle::Trace) {
Expand All @@ -628,15 +629,16 @@ bool AIE2TargetModel::isLegalTileConnection(int col, int row,
if (isBundleInList(srcBundle,
{WireBundle::DMA, WireBundle::FIFO, WireBundle::South,
WireBundle::West, WireBundle::North, WireBundle::East}))
if (isBundleInList(dstBundle,
{WireBundle::Core, WireBundle::DMA, WireBundle::Ctrl,
WireBundle::FIFO, WireBundle::South, WireBundle::West,
WireBundle::North, WireBundle::East}))
if (isBundleInList(dstBundle, {WireBundle::Core, WireBundle::DMA,
WireBundle::TileControl, WireBundle::FIFO,
WireBundle::South, WireBundle::West,
WireBundle::North, WireBundle::East}))
return (srcBundle == dstBundle) ? (srcChan == dstChan) : true;
if (srcBundle == WireBundle::Core)
return dstBundle != WireBundle::Core;
if (srcBundle == WireBundle::Ctrl)
return dstBundle != WireBundle::Ctrl && dstBundle != WireBundle::DMA;
if (srcBundle == WireBundle::TileControl)
return dstBundle != WireBundle::TileControl &&
dstBundle != WireBundle::DMA;
if (srcBundle == WireBundle::Trace) {
if (dstBundle == WireBundle::DMA)
return dstChan == 0;
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4 changes: 2 additions & 2 deletions lib/Dialect/AIE/Transforms/AIEGenerateColumnControlOverlay.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -221,7 +221,7 @@ struct AIEGenerateColumnControlOverlayPass

generatePacketFlowsForControl(
builder, device, shimTile, AIE::WireBundle::South, tilesOnCol,
AIE::WireBundle::Ctrl, 0, tileIDMap, false);
AIE::WireBundle::TileControl, 0, tileIDMap, false);
}
if (clRouteShimDmaToTileCTRL) {
// Get all tile ops on column col
Expand All @@ -234,7 +234,7 @@ struct AIEGenerateColumnControlOverlayPass

generatePacketFlowsForControl(
builder, device, shimTile, AIE::WireBundle::DMA, tilesOnCol,
AIE::WireBundle::Ctrl, 0, tileIDMap, true);
AIE::WireBundle::TileControl, 0, tileIDMap, true);
}
}
}
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8 changes: 4 additions & 4 deletions lib/Dialect/AIE/Transforms/AIEPathFinder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -195,10 +195,10 @@ void Pathfinder::initialize(int maxCol, int maxRow,
SwitchboxConnect sb = {coords};

const std::vector<WireBundle> bundles = {
WireBundle::Core, WireBundle::DMA, WireBundle::FIFO,
WireBundle::South, WireBundle::West, WireBundle::North,
WireBundle::East, WireBundle::PLIO, WireBundle::NOC,
WireBundle::Trace, WireBundle::Ctrl};
WireBundle::Core, WireBundle::DMA, WireBundle::FIFO,
WireBundle::South, WireBundle::West, WireBundle::North,
WireBundle::East, WireBundle::PLIO, WireBundle::NOC,
WireBundle::Trace, WireBundle::TileControl};
for (WireBundle bundle : bundles) {
// get all ports into current switchbox
int channels =
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