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Cleanup calls to dyn_cast #980

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Cleanup calls to dyn_cast #980

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2facdfe
Change dyn_cast to cast where applicable: include/, lib/ for AIE and …
abisca Feb 6, 2024
cd8f6df
Revert change on llvm::dyn_cast
abisca Feb 7, 2024
424dd65
Merge branch 'main' of https://github.com/Xilinx/mlir-aie into cleanup
abisca Feb 7, 2024
9716222
Format fixes
abisca Feb 7, 2024
bbc3717
Revert change
abisca Feb 7, 2024
af4be2f
Replaced dyn_cast in lib/Dialect/AIEVec
abisca Feb 7, 2024
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22 changes: 11 additions & 11 deletions lib/Dialect/AIE/IR/AIEDialect.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -656,10 +656,10 @@ std::vector<ObjectFifoCreateOp> ObjectFifoLinkOp::getInputObjectFifos() {
while ((parent = parent->getParentOp())) {
if (parent->hasTrait<OpTrait::SymbolTable>()) {
for (auto sym : getFifoIns()) {
auto name = dyn_cast<FlatSymbolRefAttr>(sym);
auto name = cast<FlatSymbolRefAttr>(sym);
if (auto *st = SymbolTable::lookupSymbolIn(parent, name);
isa_and_nonnull<ObjectFifoCreateOp>(st))
inputObjFifos.push_back(dyn_cast<ObjectFifoCreateOp>(st));
inputObjFifos.push_back(cast<ObjectFifoCreateOp>(st));
}
}
}
Expand All @@ -672,10 +672,10 @@ std::vector<ObjectFifoCreateOp> ObjectFifoLinkOp::getOutputObjectFifos() {
while ((parent = parent->getParentOp())) {
if (parent->hasTrait<OpTrait::SymbolTable>()) {
for (auto sym : getFifoOuts()) {
auto name = dyn_cast<FlatSymbolRefAttr>(sym);
auto name = cast<FlatSymbolRefAttr>(sym);
if (auto *st = SymbolTable::lookupSymbolIn(parent, name);
isa_and_nonnull<ObjectFifoCreateOp>(st))
outputObjFifos.push_back(dyn_cast<ObjectFifoCreateOp>(st));
outputObjFifos.push_back(cast<ObjectFifoCreateOp>(st));
}
}
}
Expand Down Expand Up @@ -703,7 +703,7 @@ ObjectFifoCreateOp ObjectFifoRegisterExternalBuffersOp::getObjectFifo() {
if (parent->hasTrait<OpTrait::SymbolTable>()) {
if (auto *st = SymbolTable::lookupSymbolIn(parent, getObjFifoName());
isa_and_nonnull<ObjectFifoCreateOp>(st))
return dyn_cast<ObjectFifoCreateOp>(st);
return cast<ObjectFifoCreateOp>(st);
}
}
return {};
Expand Down Expand Up @@ -759,7 +759,7 @@ ObjectFifoCreateOp ObjectFifoAcquireOp::getObjectFifo() {
if (parent->hasTrait<OpTrait::SymbolTable>()) {
if (auto *st = SymbolTable::lookupSymbolIn(parent, getObjFifoName());
isa_and_nonnull<ObjectFifoCreateOp>(st))
return dyn_cast<ObjectFifoCreateOp>(st);
return cast<ObjectFifoCreateOp>(st);
}
}
return {};
Expand Down Expand Up @@ -807,7 +807,7 @@ ObjectFifoCreateOp ObjectFifoReleaseOp::getObjectFifo() {
if (parent->hasTrait<OpTrait::SymbolTable>()) {
if (auto *st = SymbolTable::lookupSymbolIn(parent, getObjFifoName());
isa_and_nonnull<ObjectFifoCreateOp>(st))
return dyn_cast<ObjectFifoCreateOp>(st);
return cast<ObjectFifoCreateOp>(st);
}
}
return {};
Expand Down Expand Up @@ -858,7 +858,7 @@ ObjectFifoCreateOp ObjectFifoRegisterProcessOp::getObjectFifo() {
if (parent->hasTrait<OpTrait::SymbolTable>()) {
if (auto *st = SymbolTable::lookupSymbolIn(parent, getObjFifoName());
isa_and_nonnull<ObjectFifoCreateOp>(st))
return dyn_cast<ObjectFifoCreateOp>(st);
return cast<ObjectFifoCreateOp>(st);
}
}
return {};
Expand Down Expand Up @@ -1545,7 +1545,7 @@ LogicalResult SwitchboxOp::verify() {

int arbiter = -1;
for (auto val : connectOp.getAmsels()) {
auto amsel = dyn_cast<AMSelOp>(val.getDefiningOp());
auto amsel = cast<AMSelOp>(val.getDefiningOp());
if (arbiter != -1 && arbiter != amsel.arbiterIndex())
return connectOp.emitOpError(
"a master port can only be tied to one arbiter");
Expand All @@ -1564,7 +1564,7 @@ LogicalResult SwitchboxOp::verify() {
std::vector<PacketRulesOp> slvs;
for (auto *user : amselOp.getResult().getUsers()) {
if (auto s = dyn_cast<PacketRuleOp>(user)) {
auto pktRules = dyn_cast<PacketRulesOp>(s->getParentOp());
auto pktRules = cast<PacketRulesOp>(s->getParentOp());
slvs.push_back(pktRules);
} else if (auto m = dyn_cast<MasterSetOp>(user))
mstrs.push_back(m);
Expand Down Expand Up @@ -1680,7 +1680,7 @@ struct AcquireReleaseOneStateInDMABlock {
struct AccessesLocalLocks {
static LogicalResult verifyTrait(Operation *op) {
if (auto memOp = op->getParentOfType<MemOp>()) {
auto useLock = dyn_cast<UseLockOp>(op);
auto useLock = cast<UseLockOp>(op);
if (auto lock = useLock.getLockOp();
lock.getTileOp().colIndex() != memOp.colIndex() ||
lock.getTileOp().rowIndex() != memOp.rowIndex())
Expand Down
10 changes: 5 additions & 5 deletions lib/Dialect/AIE/Transforms/AIECreatePacketFlows.cpp
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Expand Up @@ -324,12 +324,12 @@ struct AIERoutePacketFlowsPass

for (Operation &Op : b.getOperations()) {
if (auto pktSource = dyn_cast<PacketSourceOp>(Op)) {
auto srcTile = dyn_cast<TileOp>(pktSource.getTile().getDefiningOp());
auto srcTile = cast<TileOp>(pktSource.getTile().getDefiningOp());
xSrc = srcTile.colIndex();
ySrc = srcTile.rowIndex();
sourcePort = pktSource.port();
} else if (auto pktDest = dyn_cast<PacketDestOp>(Op)) {
auto destTile = dyn_cast<TileOp>(pktDest.getTile().getDefiningOp());
auto destTile = cast<TileOp>(pktDest.getTile().getDefiningOp());
int xDest = destTile.colIndex();
int yDest = destTile.rowIndex();
Port destPort = pktDest.port();
Expand Down Expand Up @@ -487,7 +487,7 @@ struct AIERoutePacketFlowsPass
WireBundle bundle = physPort.second.bundle;
int channel = physPort.second.channel;
assert(tileOp);
auto tile = dyn_cast<TileOp>(tileOp);
auto tile = cast<TileOp>(tileOp);
LLVM_DEBUG(llvm::dbgs()
<< "master " << tile << " " << stringifyWireBundle(bundle)
<< " : " << channel << '\n');
Expand Down Expand Up @@ -571,7 +571,7 @@ struct AIERoutePacketFlowsPass
LLVM_DEBUG(llvm::dbgs() << "CHECK Slave Masks\n");
for (auto map : slaveMasks) {
auto port = map.first.first;
auto tile = dyn_cast<TileOp>(port.first);
auto tile = cast<TileOp>(port.first);
WireBundle bundle = port.second.bundle;
int channel = port.second.channel;
int ID = map.first.second;
Expand All @@ -595,7 +595,7 @@ struct AIERoutePacketFlowsPass
// Realize the routes in MLIR
for (auto map : tiles) {
Operation *tileOp = map.second;
auto tile = dyn_cast<TileOp>(tileOp);
auto tile = cast<TileOp>(tileOp);

// Create a switchbox for the routes and insert inside it.
builder.setInsertionPointAfter(tileOp);
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/AIE/Transforms/AIELocalizeLocks.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ struct AIELocalizeLocksPass : AIELocalizeLocksBase<AIELocalizeLocksPass> {
// Collect the locks used in this core.
const auto &targetModel = getTargetModel(coreOp);

auto thisTile = dyn_cast<TileOp>(coreOp.getTile().getDefiningOp());
auto thisTile = cast<TileOp>(coreOp.getTile().getDefiningOp());
int col = thisTile.colIndex();
int row = thisTile.rowIndex();

Expand Down
6 changes: 3 additions & 3 deletions lib/Dialect/AIE/Transforms/AIEObjectFifoStatefulTransform.cpp
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Expand Up @@ -367,7 +367,7 @@ struct AIEObjectFifoStatefulTransformPass
creation_tile = op.getProducerTileOp();
else {
auto consumerTileOp =
dyn_cast<TileOp>(op.getConsumerTiles()[0].getDefiningOp());
cast<TileOp>(op.getConsumerTiles()[0].getDefiningOp());
creation_tile = consumerTileOp;
}

Expand Down Expand Up @@ -1200,7 +1200,7 @@ struct AIEObjectFifoStatefulTransformPass
continue;

for (auto consumerTile : createOp.getConsumerTiles()) {
auto consumerTileOp = dyn_cast<TileOp>(consumerTile.getDefiningOp());
auto consumerTileOp = cast<TileOp>(consumerTile.getDefiningOp());

if (isa<ArrayAttr>(createOp.getElemNumber())) {
// +1 to account for 1st depth (producer)
Expand Down Expand Up @@ -1273,7 +1273,7 @@ struct AIEObjectFifoStatefulTransformPass
// loop unrolling pass
objectFifoTiles.insert(createOp.getProducerTileOp());
for (auto consumerTile : createOp.getConsumerTiles()) {
auto consumerTileOp = dyn_cast<TileOp>(consumerTile.getDefiningOp());
auto consumerTileOp = cast<TileOp>(consumerTile.getDefiningOp());
objectFifoTiles.insert(consumerTileOp);
}

Expand Down
4 changes: 2 additions & 2 deletions lib/Dialect/AIEVec/IR/AIEVecOps.cpp
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Expand Up @@ -1171,14 +1171,14 @@ ConcatOp::inferReturnTypes(MLIRContext *, std::optional<Location>,
adaptor.getSources().end());
unsigned totalLength = 0;
for (auto source : srcs) {
VectorType type = llvm::dyn_cast<VectorType>(source.getType());
VectorType type = llvm::cast<VectorType>(source.getType());
assert(type.getRank() == 1 &&
"only rank 1 vectors currently supported by concat");
totalLength += type.getDimSize(0);
}
inferredReturnTypes.push_back(VectorType::get(
{totalLength},
srcs[0].getType().dyn_cast<VectorType>().getElementType()));
srcs[0].getType().cast<VectorType>().getElementType()));
Comment on lines 1180 to +1181
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[clang-format] reported by reviewdog 🐶

Suggested change
{totalLength},
srcs[0].getType().dyn_cast<VectorType>().getElementType()));
srcs[0].getType().cast<VectorType>().getElementType()));
{totalLength}, srcs[0].getType().cast<VectorType>().getElementType()));

return success();
}

Expand Down
8 changes: 4 additions & 4 deletions lib/Dialect/AIEVec/Transforms/AIEVectorize.cpp
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Expand Up @@ -2185,17 +2185,17 @@ static void fuseMulFMAOpsForInt16(Operation *Op, VectState *state) {
// lhs of current FMAOp should be an upd operation with 512-bit vector width.
// For AIE-ML, we can directly load 512 bits vectors. Thus, we can delete the
// upd operation with index 1.
auto lUpdOp = dyn_cast<aievec::UPDOp>(lhs.getDefiningOp());
auto lUpdOp = cast<aievec::UPDOp>(lhs.getDefiningOp());
if (lUpdOp.getIndex() == 1) {
auto lUpdOp0 = dyn_cast<aievec::UPDOp>(lUpdOp.getVector().getDefiningOp());
auto lUpdOp0 = cast<aievec::UPDOp>(lUpdOp.getVector().getDefiningOp());
lUpdOp->replaceAllUsesWith(lUpdOp0);
lUpdOp->erase();
}

// 2. Deal with the rhs:
// Since vector size of current FMAOp rhs is 256 bits, we need to generate a
// concat op to make the vector size to 512 bits.
auto rUpdOp = dyn_cast<aievec::UPDOp>(curOp->getOperand(1).getDefiningOp());
auto rUpdOp = cast<aievec::UPDOp>(curOp->getOperand(1).getDefiningOp());
state->builder.setInsertionPointAfter(rUpdOp);
AIEVecAttributes rstat = getOperandVecStats(curOp, state, 1);
assert(rstat.vecSizeInBits % 256 == 0);
Expand All @@ -2212,7 +2212,7 @@ static void fuseMulFMAOpsForInt16(Operation *Op, VectState *state) {
Operation *convOp = nullptr;
Operation *mulOrFMAOp = Op->getOperand(2).getDefiningOp();
auto mulOp = dyn_cast<aievec::MulOp>(mulOrFMAOp);
auto fmaOp = dyn_cast<aievec::FMAOp>(mulOrFMAOp);
auto fmaOp = cast<aievec::FMAOp>(mulOrFMAOp);
int32_t zStart;

if (mulOp) {
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/AIEVec/Transforms/FoldMulAddChainToConvOp.cpp
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Expand Up @@ -266,7 +266,7 @@ struct LongestConvMACChainAnalysis {
isa<aievec::ExtOp>(opBwdSlices[sliceSz - 1]))) {
convMacRhs = opBwdSlices[sliceSz - 3]->getOperand(0);
convMacBcastIdx =
dyn_cast<aievec::BroadcastOp>(opBwdSlices[sliceSz - 2]).getIdx();
cast<aievec::BroadcastOp>(opBwdSlices[sliceSz - 2]).getIdx();
return true;
}
}
Expand Down
14 changes: 7 additions & 7 deletions lib/Dialect/AIEVec/Transforms/VectorToAIEVecConversions.cpp
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Expand Up @@ -380,7 +380,7 @@ static void generateAIEVecOpsForReductionOp(ConversionPatternRewriter &rewriter,
"shiftIndex must be power of 2");

Location loc = srcOp.getLoc();
auto vType = dyn_cast<VectorType>(curValue.getType());
auto vType = cast<VectorType>(curValue.getType());
Type scalarType = vType.getElementType();
Type vecType = curValue.getType();
DstOpTy curOp = nullptr;
Expand Down Expand Up @@ -1341,7 +1341,7 @@ struct LowerVectorCmpOpToAIEVecCmpOp : OpConversionPattern<SrcOpTy> {
if (!aieCmpOp)
return failure();

VectorType resultType = dyn_cast<VectorType>(srcOp.getResult().getType());
VectorType resultType = cast<VectorType>(srcOp.getResult().getType());
// Convert vector i1 type to unsigned interger type by built-in unrealized
// conversion cast op.
rewriter.replaceOpWithNewOp<UnrealizedConversionCastOp>(
Expand Down Expand Up @@ -1571,7 +1571,7 @@ struct LowerVectorReductionAddBfloat16Op
Location loc = srcOp.getLoc();
Type accType = getVectorOpDestType(vType, /*AIEML =*/true);
unsigned accWidth =
dyn_cast<VectorType>(accType).getElementType().getIntOrFloatBitWidth();
cast<VectorType>(accType).getElementType().getIntOrFloatBitWidth();

auto upsOp =
rewriter.create<aievec::UPSOp>(loc, accType, srcOp.getVector());
Expand Down Expand Up @@ -2026,8 +2026,8 @@ struct LowerExtOpPattern : OpConversionPattern<SrcOpTy> {
LogicalResult
matchAndRewrite(SrcOpTy extOp, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
VectorType srcType = dyn_cast<VectorType>(extOp.getIn().getType());
VectorType dstType = dyn_cast<VectorType>(extOp.getOut().getType());
VectorType srcType = cast<VectorType>(extOp.getIn().getType());
VectorType dstType = cast<VectorType>(extOp.getOut().getType());

auto accType = getVectorOpDestType(srcType, /*AIEML =*/true);
auto upsOp =
Expand Down Expand Up @@ -2057,8 +2057,8 @@ struct LowerTruncOpPattern : OpConversionPattern<SrcOpTy> {
LogicalResult
matchAndRewrite(SrcOpTy truncOp, OpAdaptor adaptor,
ConversionPatternRewriter &rewriter) const override {
VectorType srcType = dyn_cast<VectorType>(truncOp.getIn().getType());
VectorType dstType = dyn_cast<VectorType>(truncOp.getOut().getType());
VectorType srcType = cast<VectorType>(truncOp.getIn().getType());
VectorType dstType = cast<VectorType>(truncOp.getOut().getType());
Type scalarType = srcType.getElementType();
unsigned elWidth = scalarType.getIntOrFloatBitWidth();

Expand Down
6 changes: 2 additions & 4 deletions lib/Dialect/AIEX/Transforms/AIECreateBroadcastPacket.cpp
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Expand Up @@ -56,8 +56,7 @@ struct AIEBroadcastPacketPass
Region &r = broadcastpacket.getPorts();
Block &b = r.front();
Port sourcePort = broadcastpacket.port();
TileOp srcTile =
dyn_cast<TileOp>(broadcastpacket.getTile().getDefiningOp());
TileOp srcTile = cast<TileOp>(broadcastpacket.getTile().getDefiningOp());

for (Operation &Op : b.getOperations()) {
if (BPIDOp bpid = dyn_cast<BPIDOp>(Op)) {
Expand All @@ -74,8 +73,7 @@ struct AIEBroadcastPacketPass
sourcePort.bundle, sourcePort.channel);
for (Operation &op : b_bpid.getOperations()) {
if (BPDestOp bpdest = dyn_cast<BPDestOp>(op)) {
TileOp destTile =
dyn_cast<TileOp>(bpdest.getTile().getDefiningOp());
TileOp destTile = cast<TileOp>(bpdest.getTile().getDefiningOp());
Port destPort = bpdest.port();
builder.setInsertionPointToEnd(b_pkFlow);
builder.create<PacketDestOp>(builder.getUnknownLoc(), destTile,
Expand Down
6 changes: 3 additions & 3 deletions lib/Dialect/AIEX/Transforms/AIECreateCores.cpp
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Expand Up @@ -105,7 +105,7 @@ struct AIECreateCoresPass : public AIECreateCoresBase<AIECreateCoresPass> {
tiles[{colIndex, rowIndex}] = tile;
}
Operation *tileOp = tiles[{colIndex, rowIndex}];
TileOp tile = dyn_cast<TileOp>(tileOp);
TileOp tile = cast<TileOp>(tileOp);
builder.setInsertionPointAfter(tileOp);

// create MemOp
Expand Down Expand Up @@ -216,8 +216,8 @@ struct AIECreateCoresPass : public AIECreateCoresBase<AIECreateCoresPass> {
// DenseMap<Value, int> destChannel;
// for (auto op : device.getOps<MemcpyOp>()) {
// builder.setInsertionPoint(op);
// TileOp srcTile = dyn_cast<TileOp>(op.srcTile().getDefiningOp());
// TileOp dstTile = dyn_cast<TileOp>(op.dstTile().getDefiningOp());
// TileOp srcTile = cast<TileOp>(op.srcTile().getDefiningOp());
// TileOp dstTile = cast<TileOp>(op.dstTile().getDefiningOp());
// // TODO: perhaps a better approach is to not assert here, but rather
// have a subsequent pass
// // that legally relocates the ports
Expand Down
2 changes: 1 addition & 1 deletion lib/Dialect/AIEX/Transforms/AIECreateLocks.cpp
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Expand Up @@ -192,7 +192,7 @@ struct AIECreateLocksPass : public AIECreateLocksBase<AIECreateLocksPass> {
assert(tileOp &&
"Sorry, the lock users of this chain do not have a common lock");

TileOp tile = dyn_cast<TileOp>(tileOp);
TileOp tile = cast<TileOp>(tileOp);
int lockID = getLockID(locks, tileOp);
assert(lockID >= 0 && "No more locks to allocate!");
LLVM_DEBUG(llvm::dbgs() << "Shared tile \n"; tileOp->print(llvm::dbgs()));
Expand Down
22 changes: 9 additions & 13 deletions lib/Dialect/AIEX/Transforms/AIEHerdRouting.cpp
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Expand Up @@ -217,25 +217,21 @@ struct AIEHerdRoutingPass : AIEHerdRoutingBase<AIEHerdRoutingPass> {
routeOps.push_back(routeOp);

auto sourceHerds =
dyn_cast<SelectOp>(routeOp.getSourceHerds().getDefiningOp());
auto destHerds =
dyn_cast<SelectOp>(routeOp.getDestHerds().getDefiningOp());
cast<SelectOp>(routeOp.getSourceHerds().getDefiningOp());
auto destHerds = cast<SelectOp>(routeOp.getDestHerds().getDefiningOp());
WireBundle sourceBundle = routeOp.getSourceBundle();
WireBundle destBundle = routeOp.getDestBundle();
int sourceChannel = routeOp.getSourceChannelValue();
int destChannel = routeOp.getDestChannelValue();

HerdOp sourceHerd =
dyn_cast<HerdOp>(sourceHerds.getStartHerd().getDefiningOp());
IterOp sourceIterX =
dyn_cast<IterOp>(sourceHerds.getIterX().getDefiningOp());
IterOp sourceIterY =
dyn_cast<IterOp>(sourceHerds.getIterY().getDefiningOp());
cast<HerdOp>(sourceHerds.getStartHerd().getDefiningOp());
IterOp sourceIterX = cast<IterOp>(sourceHerds.getIterX().getDefiningOp());
IterOp sourceIterY = cast<IterOp>(sourceHerds.getIterY().getDefiningOp());

HerdOp destHerd =
dyn_cast<HerdOp>(destHerds.getStartHerd().getDefiningOp());
IterOp destIterX = dyn_cast<IterOp>(destHerds.getIterX().getDefiningOp());
IterOp destIterY = dyn_cast<IterOp>(destHerds.getIterY().getDefiningOp());
HerdOp destHerd = cast<HerdOp>(destHerds.getStartHerd().getDefiningOp());
IterOp destIterX = cast<IterOp>(destHerds.getIterX().getDefiningOp());
IterOp destIterY = cast<IterOp>(destHerds.getIterY().getDefiningOp());

int sourceStartX = sourceIterX.getStartValue();
int sourceEndX = sourceIterX.getEndValue();
Expand Down Expand Up @@ -293,7 +289,7 @@ struct AIEHerdRoutingPass : AIEHerdRoutingBase<AIEHerdRoutingPass> {
int x = swboxCfg.first.second.col;
int y = swboxCfg.first.second.row;
auto connects = swboxCfg.second;
HerdOp herd = dyn_cast<HerdOp>(herdOp);
HerdOp herd = cast<HerdOp>(herdOp);

builder.setInsertionPoint(device.getBody()->getTerminator());

Expand Down
4 changes: 2 additions & 2 deletions lib/Dialect/AIEX/Transforms/AIELowerMemcpy.cpp
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Expand Up @@ -113,8 +113,8 @@ struct AIELowerMemcpyPass : public AIELowerMemcpyBase<AIELowerMemcpyPass> {
DenseMap<Value, int> destChannel;
for (auto op : device.getOps<MemcpyOp>()) {
builder.setInsertionPoint(op);
TileOp srcTile = dyn_cast<TileOp>(op.getSrcTile().getDefiningOp());
TileOp dstTile = dyn_cast<TileOp>(op.getDstTile().getDefiningOp());
TileOp srcTile = cast<TileOp>(op.getSrcTile().getDefiningOp());
TileOp dstTile = cast<TileOp>(op.getDstTile().getDefiningOp());
// TODO: perhaps a better approach is to not assert here, but rather have
// a subsequent pass that legally relocates the ports
assert(destChannel[op.getDstTile()] <= 2 &&
Expand Down
5 changes: 2 additions & 3 deletions lib/Dialect/AIEX/Transforms/AIELowerMulticast.cpp
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Expand Up @@ -55,11 +55,10 @@ struct AIELowerMulticastPass : public AIEMulticastBase<AIELowerMulticastPass> {
Region &r = multicast.getPorts();
Block &b = r.front();
Port sourcePort = multicast.port();
TileOp srcTile = dyn_cast<TileOp>(multicast.getTile().getDefiningOp());
TileOp srcTile = cast<TileOp>(multicast.getTile().getDefiningOp());
for (Operation &Op : b.getOperations()) {
if (MultiDestOp multiDest = dyn_cast<MultiDestOp>(Op)) {
TileOp destTile =
dyn_cast<TileOp>(multiDest.getTile().getDefiningOp());
TileOp destTile = cast<TileOp>(multiDest.getTile().getDefiningOp());
Port destPort = multiDest.port();
builder.create<FlowOp>(builder.getUnknownLoc(), srcTile,
sourcePort.bundle, sourcePort.channel,
Expand Down
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