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Merged
merged 1 commit into from
Oct 26, 2024
+35 −35
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nall: Namespace noinline macro #1674

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4 changes: 2 additions & 2 deletions ares/component/processor/gsu/gsu.hpp
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Expand Up @@ -75,8 +75,8 @@ struct GSU {
auto serialize(serializer&) -> void;

//disassembler.cpp
noinline auto disassembleInstruction() -> string;
noinline auto disassembleContext() -> string;
NALL_NOINLINE auto disassembleInstruction() -> string;
NALL_NOINLINE auto disassembleContext() -> string;

auto disassembleOpcode(char* output) -> void;
auto disassembleALT0(char* output) -> void;
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4 changes: 2 additions & 2 deletions ares/component/processor/hg51b/hg51b.hpp
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Expand Up @@ -111,8 +111,8 @@ struct HG51B {
auto writeRegister(n7 address, n24 data) -> void;

//disassembler.cpp
noinline auto disassembleInstruction(maybe<n15> pb = {}, maybe<n8> pc = {}) -> string;
noinline auto disassembleContext() -> string;
NALL_NOINLINE auto disassembleInstruction(maybe<n15> pb = {}, maybe<n8> pc = {}) -> string;
NALL_NOINLINE auto disassembleContext() -> string;

protected:
struct Registers {
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4 changes: 2 additions & 2 deletions ares/component/processor/i8080/i8080.hpp
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Expand Up @@ -124,8 +124,8 @@ struct I8080 {
auto serialize(serializer&) -> void;

//disassembler.cpp
noinline auto disassembleInstruction(maybe<n16> pc = {}) -> string;
noinline auto disassembleContext() -> string;
NALL_NOINLINE auto disassembleInstruction(maybe<n16> pc = {}) -> string;
NALL_NOINLINE auto disassembleContext() -> string;

auto disassemble(n16 pc, n8 prefix, n8 code) -> string;

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4 changes: 2 additions & 2 deletions ares/component/processor/mos6502/mos6502.hpp
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Expand Up @@ -156,8 +156,8 @@ struct MOS6502 {
auto serialize(serializer&) -> void;

//disassembler.cpp
noinline auto disassembleInstruction(maybe<n16> pc = {}) -> string;
noinline auto disassembleContext() -> string;
NALL_NOINLINE auto disassembleInstruction(maybe<n16> pc = {}) -> string;
NALL_NOINLINE auto disassembleContext() -> string;

struct PR {
bool c; //carry
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6 changes: 3 additions & 3 deletions ares/component/processor/sh2/instructions.cpp
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Expand Up @@ -513,19 +513,19 @@ auto SH2::MOVI(u32 i, u32 n) -> void {
}

//MOV.W @(disp,PC),Rn
noinline auto SH2::MOVWI(u32 d, u32 n) -> void {
NALL_NOINLINE auto SH2::MOVWI(u32 d, u32 n) -> void {
u32 pc = inDelaySlot() ? PPC - 2 : PC;
R[n] = (s16)readWord(pc + d * 2);
}

//MOV.L @(disp,PC),Rn
noinline auto SH2::MOVLI(u32 d, u32 n) -> void {
NALL_NOINLINE auto SH2::MOVLI(u32 d, u32 n) -> void {
u32 pc = inDelaySlot() ? PPC - 2 : PC;
R[n] = readLong((pc & ~3) + d * 4);
}

//MOVA @(disp,PC),R0
noinline auto SH2::MOVA(u32 d) -> void {
NALL_NOINLINE auto SH2::MOVA(u32 d) -> void {
u32 pc = inDelaySlot() ? PPC - 2 : PC;
R[0] = (pc & ~3) + d * 4;
}
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4 changes: 2 additions & 2 deletions ares/component/processor/sm83/sm83.hpp
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Expand Up @@ -29,8 +29,8 @@ struct SM83 {

//disassembler.cpp
virtual auto readDebugger(n16 address) -> n8 { return 0; }
noinline auto disassembleInstruction(maybe<n16> pc = {}) -> string;
noinline auto disassembleContext() -> string;
NALL_NOINLINE auto disassembleInstruction(maybe<n16> pc = {}) -> string;
NALL_NOINLINE auto disassembleContext() -> string;

//memory.cpp
auto operand() -> n8;
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6 changes: 3 additions & 3 deletions ares/component/processor/spc700/spc700.hpp
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Expand Up @@ -117,9 +117,9 @@ struct SPC700 {
auto serialize(serializer&) -> void;

//disassembler.cpp
noinline auto disassembleInstruction(n16 address, n1 p) -> string;
noinline auto disassembleInstruction() -> string;
noinline auto disassembleContext() -> string;
NALL_NOINLINE auto disassembleInstruction(n16 address, n1 p) -> string;
NALL_NOINLINE auto disassembleInstruction() -> string;
NALL_NOINLINE auto disassembleContext() -> string;

struct Flags {
bool c; //carry
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4 changes: 2 additions & 2 deletions ares/component/processor/tlcs900h/disassembler.cpp
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@@ -1,4 +1,4 @@
noinline auto TLCS900H::disassembleInstruction() -> string {
NALL_NOINLINE auto TLCS900H::disassembleInstruction() -> string {
string output;

auto pc = load(PC);
Expand Down Expand Up @@ -636,7 +636,7 @@ noinline auto TLCS900H::disassembleInstruction() -> string {
return pad(output, -48);
}

noinline auto TLCS900H::disassembleContext() -> string {
NALL_NOINLINE auto TLCS900H::disassembleContext() -> string {
string output;
output.append("XWA:", hex(r.xwa[RFP].l.l0, 8L), " ");
output.append("XBC:", hex(r.xbc[RFP].l.l0, 8L), " ");
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4 changes: 2 additions & 2 deletions ares/component/processor/upd96050/upd96050.hpp
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Expand Up @@ -25,8 +25,8 @@ struct uPD96050 {
auto writeDP(n12 address, n8 data) -> void;

//disassembler.cpp
noinline auto disassembleInstruction(maybe<n14> ip = {}) -> string;
noinline auto disassembleContext() -> string;
NALL_NOINLINE auto disassembleInstruction(maybe<n14> ip = {}) -> string;
NALL_NOINLINE auto disassembleContext() -> string;

enum class Revision : u32 { uPD7725, uPD96050 } revision;
n24 programROM[16384];
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6 changes: 3 additions & 3 deletions ares/component/processor/wdc65816/wdc65816.hpp
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Expand Up @@ -235,9 +235,9 @@ struct WDC65816 {
auto serialize(serializer&) -> void;

//disassembler.cpp
noinline auto disassembleInstruction(n24 address, bool e, bool m, bool x) -> string;
noinline auto disassembleInstruction() -> string;
noinline auto disassembleContext(maybe<bool> e = {}) -> string;
NALL_NOINLINE auto disassembleInstruction(n24 address, bool e, bool m, bool x) -> string;
NALL_NOINLINE auto disassembleInstruction() -> string;
NALL_NOINLINE auto disassembleContext(maybe<bool> e = {}) -> string;

struct f8 {
bool c = 0; //carry
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4 changes: 2 additions & 2 deletions ares/component/processor/z80/z80.hpp
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Expand Up @@ -211,8 +211,8 @@ struct Z80 {
auto serialize(serializer&) -> void;

//disassembler.cpp
noinline auto disassembleInstruction(maybe<n16> pc = {}) -> string;
noinline auto disassembleContext() -> string;
NALL_NOINLINE auto disassembleInstruction(maybe<n16> pc = {}) -> string;
NALL_NOINLINE auto disassembleContext() -> string;

auto disassemble(n16 pc, n8 prefix, n8 code) -> string;
auto disassembleCB(n16 pc, n8 prefix, n8 code) -> string;
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2 changes: 1 addition & 1 deletion ares/n64/cpu/interpreter-fpu.cpp
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Expand Up @@ -250,7 +250,7 @@ auto CPU::checkFPUExceptions() -> bool {

#define CHECK_FPE_IMPL(type, res, operation, convert) \
fenv.clearExcept(); \
volatile type v##res = [&]() noinline -> type { return operation; }(); \
volatile type v##res = [&]() NALL_NOINLINE -> type { return operation; }(); \
if (checkFPUExceptions<convert>()) return; \
type res = v##res;

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12 changes: 6 additions & 6 deletions ares/sfc/ppu/ppu.hpp
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Expand Up @@ -90,12 +90,12 @@ struct PPU : PPUBase::Implementation, PPUcounter {

//main.cpp
auto main() -> void;
noinline auto cycleObjectEvaluate() -> void;
template<u32 Cycle> noinline auto cycleBackgroundFetch() -> void;
noinline auto cycleBackgroundBegin() -> void;
noinline auto cycleBackgroundBelow() -> void;
noinline auto cycleBackgroundAbove() -> void;
noinline auto cycleRenderPixel() -> void;
NALL_NOINLINE auto cycleObjectEvaluate() -> void;
template<u32 Cycle> NALL_NOINLINE auto cycleBackgroundFetch() -> void;
NALL_NOINLINE auto cycleBackgroundBegin() -> void;
NALL_NOINLINE auto cycleBackgroundBelow() -> void;
NALL_NOINLINE auto cycleBackgroundAbove() -> void;
NALL_NOINLINE auto cycleRenderPixel() -> void;
template<u32> auto cycle() -> void;

//io.cpp
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6 changes: 3 additions & 3 deletions nall/platform.hpp
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Expand Up @@ -161,15 +161,15 @@ namespace nall {

#if defined(COMPILER_CLANG) || defined(COMPILER_GCC)
#define no_optimize __attribute__((optnone))
#define noinline __attribute__((noinline))
#define NALL_NOINLINE __attribute__((noinline))
#define alwaysinline inline __attribute__((always_inline))
#elif defined(COMPILER_MICROSOFT)
#define no_optimize
#define noinline __declspec(noinline)
#define NALL_NOINLINE __declspec(noinline)
#define alwaysinline inline __forceinline
#else
#define no_optimize
#define noinline
#define NALL_NOINLINE
#define alwaysinline inline
#endif

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