[DOC] Port Spec Updates to 2.0 patch release #796
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calebofearth
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Oct 3, 2025
calebofearth
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Oct 10, 2025
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* Update late binding interface signals section MCI generic input wires are allowed to be used by the SOC. * Add MCU Mailbox Doorbell Command DLEN section * Add MCU MBOX DLEN 0 clears entire MBOX SRAM * Add external staging area base address input * Fix typo in note about MBOX SRAM clearing * Revise mci_generic_input/output wires allocation details * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <[email protected]> * Correct capitalization of 'Chips Alliance' to 'CHIPS Alliance' --------- Co-authored-by: Copilot <[email protected]>
* [DOC] Add MCU customization * Clean up README by removing configuration examples Removed common configuration examples and troubleshooting tips from README.
* [DOC] Add MCU iCache requirements * Fix spelling and clarify MCU iCache requirements Corrected spelling errors and clarified MCU iCache integration requirements. * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Copilot <[email protected]> * [Doc] Add DCCM sizing note * Update docs/CaliptraSSIntegrationSpecification.md Co-authored-by: Christopher Swenson <[email protected]> * Modify MCI Register Space mapping requirements Updated MCI Register Space mapping to enable side effects. * Add side effect info for SRAMs used by MCU * Update DWORD access requirements in specification Clarified DWORD access requirements and split memory mapping options. --------- Co-authored-by: Copilot <[email protected]> Co-authored-by: Christopher Swenson <[email protected]>
Co-authored-by: Caleb <[email protected]>
Co-authored-by: Caleb <[email protected]>
Co-authored-by: Caleb <[email protected]>
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calebofearth
approved these changes
Oct 10, 2025
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