Caliptra Subsystem Gen 2.1 Release

Overview

Release for Caliptra Subsystem version 2.1 RTL. All features are completed, verification plans are executed and signed-off, documentation has been updated, and first cut runs of CDC, Lint, RDC, Synthesis runs are clean.

Release Notes

What's Changed

• [VAL] Fix function call (num args) to soc_ifc_axi_dma_send_axi_to_axi by @calebofearth in #708
• [RTL] Blocking MCU Reads on UDS/FE just before Locking by @ekarabu in #710
• [fuse_ctrl, dv] Complete fuse_ctrl zeroization top-level assertions by @martin-velay in #709
• Update integration and HW spec by @clayton8 in #734
• [Doc] Fixed #643 & Added AXI Streaming boot test by @nileshbpat in #735
• Add ratchet_seed_lock_en test by @antmarzam in #685
• [DOC] Add MCU Customization by @clayton8 in #748
• [DOC] Add additional lint exceptions by @clayton8 in #765
• Lowrisc fc obfuscate zeroization res by @antmarzam in #754
• [fuse_ctrl,dv] Assorted cleanups to how FC tests look at magic registers by @rswarbrick in #750
• [DOC] Add MCU icache and DCCM sizing requirements by @clayton8 in #771
• [DOC] Add Zeroize command to Integration spec by @andreaskurth in #770
• [fuse_ctrl,dv] Improvements to wait_dai_op_idle by @rswarbrick in #751
• [fuse_ctrl,dv] lowRISC change bundle 0 by @rswarbrick in #774
• [RTL] i3c core rev update to v1p3 rc patch, setdasa bug fix by @nileshbpat in #783
• Collected lowRISC changes: bundle 1 by @rswarbrick in #786
• [fuse_ctrl, dv] Add assertions related to RTL change to obfuscate zeroization result by @martin-velay in #791
• [RTL] Make lc_ctrl RAW unlock token a caliptra_ss_top input signal by @andreaskurth in #782
• [DOC] Integrator Responsibilities for Fuse Zeroization by @ekarabu in #795
• [INFRA] Updated environment variable for issue #240 by @nileshbpat in #797
• [DOC] Clarify AXI interface usage in Caliptra Core for Lint by @clayton8 in #802
• [RTL][DOC] Update HW_REV_ID to 2.1, add Release Process doc, update register pages gen workflow by @calebofearth in #798
• [RTL,VAL] Change lc_ctrl RAW unlock token and document integration by @andreaskurth in #792
• [TB] update jtag listening ports to ephemeral range by @Nitsirks in #803
• lowRISC change bundle 3 by @rswarbrick in #799
• lowRISC change bundle 3.5 by @rswarbrick in #806
• lowRISC change bundle 4 by @rswarbrick in #801
• [RTL] Upgrade VeeR RV core and caliptra-rtl submodule to fix AHB bug and lint issues by @calebofearth in #809
• [DOC] Update known lint issues in CaliptraSSIntegrationSpecification.md by @clayton8 in #814
• SHA3 coverage analysis by @marnovandermaas in #759
• lowRISC change bundle 6 by @andreaskurth in #812
• Add define to get FSMs recognised in coverage reports by @rswarbrick in #813
• [RTL] caliptra-rtl submodule update to v2.1 release version by @calebofearth in #819
• [DOC] Final documentation updates for 2.1 release by @calebofearth in #820

New Contributors

• @martin-velay made their first contribution in #709
• @rswarbrick made their first contribution in #750

Full Changelog: css-gen2.1-v1.0-rc1...css-v2.1

Caliptra Subsystem Gen 2.1 Release v1p0 Release Candidate

Official Caliptra Subsystem Gen 2.1 Release v1p0 RC1

Overview

Release for Caliptra Subsystem Gen 2.1 RTL, version 1p0 RC1. All features are completed, verification plans are executed and signed-off, documentation has been updated, and first cut runs of CDC, Lint, RDC, Synthesis runs are clean.

Release Notes

What's Changed

• [VAL] Remove FIXMEs by @clayton8 in #415
• [DOC] Mention MCU MBOX SRAM accesses must be DWORD accesses by @clayton8 in #413
• [VAL] Test fixes for MCI Register Validation by @anjpar in #423
• [DOC] Spec clarifications by @clayton8 in #425
• [VAL] Fix randomization for mask select and SVA conditions by @upadhyayulakiran in #417
• [RTL] I3C Core rev update to tag v1p1 by @nileshbpat in #424
• [ENV] Kick off JTAG tests in parallel by @clayton8 in #434
• [DOC] Open test plan permissions; clarify SRAM requirement in spec by @calebofearth in #431
• [ENV] Remove submit JTAG script and add new JTAG TL by @clayton8 in #445
• [DOC] Fix issue Question regarding clock frequency #426 by @nileshbpat in #450
• [VAL] Add MCI cacheable test-case (not included in regr yet); tweak some C lib behavior by @calebofearth in #449
• [DOC] Add clarification on AXI DMA routes to SS HW spec by @calebofearth in #456
• [VAL] Minor fixes for MCI register tests by @anjpar in #460
• [DOC] Fix markdown syntax issue in HW spec by @calebofearth in #468
• [DOC] Add FIPS zeroization to generic input wires by @clayton8 in #473
• [DOC] Fix broken hyperlink in SS integration spec by @calebofearth in #469
• [DOC] Clarify AXI interconnect requirements in SS integration spec by @calebofearth in #477
• [fuse_ctrl, tools] Include pyyaml in requirements.txt by @andrea-caforio in #471
• [fuse_ctrl, test] Generate mmap header for testsuite by @andrea-caforio in #466
• GH Issue fixes by @nileshbpat in #480
• [TB] Coverage Dashboard Draft and test addition by @nileshbpat in #494
• Link update to coverage draft by @nileshbpat in #496
• User/ekarabulut/otp optional items by @ekarabu in #483
• [VAL][SVA] MCI Register test fixes and WDT Timer assertions fix by @anjpar in #497
• [TB] Add missing MCI coverage by @clayton8 in #500
• [SPEC] Update CSS memory map by @clayton8 in #522
• [Cov] Added Caliptra SS coverage updates by @nileshbpat in #526
• [RTL] Fix coverage miss bug due to missing parentheses by @anjpar in #529
• [RTL] Expose I3C SB signals for external I3C bypass boot, connect scan_mode to MCU, and spec updates by @clayton8 in #537
• [RTL] Fix MCU scan mode by @clayton8 in #553
• [DOC][VAL] Disconnect MCU ROM wr path in TB; clarify MCU ROM if connection req and SRAM error handling sections by @calebofearth in #550
• [DOC] Add Caliptra Core coverage analysis by @calebofearth in #543
• Coverage updates and fixed gh484 by @nileshbpat in #565
• [Cov] Coverage Doc Updates by @nileshbpat in #574
• [fuse_ctrl] Word-align fuse addresses by @andrea-caforio in #548
• [RTL] Expose RDC Related Signals 2.0 by @clayton8 in #580
• [VAL] Fix incorrect pointer in mci FW test by @anjpar in #573
• [BUG FIX] Drive a_data with zeroes for reads instead of wdata, which may be arbitrary by @calebofearth in #590
• pointed caliptra_v_2_0_1 branch by @ekarabu in #612
• [VAL] Update testbench to exercise SHA accelerator endian-swap feature in streaming mode by @calebofearth in #544
• [RTL] Update I3C Submodule and Add connections for cio_test* signals by @nileshbpat in #629
• Dev 2.1 by @clayton8 in #631
• document update for LCC and FC by @ekarabu in #641
• [RTL] Integrate OCP LOCK from caliptra-rtl by @clayton8 in #638
• [RTL] Update I3C rev to v1p3-rc by @nileshbpat in #642
• [TB] FIXME/TODO cleanup and TB runtime improvements by @clayton8 in #646
• [TB+VAL] UDS update on Straps by @ekarabu in #648
• [VAL] I3C Tests update by @nileshbpat in #651
• [RTL+VAL] updated caliptra-rtl by @ekarabu in #652
• brought out strap to ss top by @ekarabu in #654
• Update caliptra-rtl by @clayton8 in #655
• Update calipitra-rtl by @clayton8 in #659
• Update caliptra-rtl by @clayton8 in #662
• updated i3c version by @ekarabu in #666
• [fuse_ctrl] Zeroization by @andrea-caforio in #518
• [RTL+TB]Update caliptra-rtl version to 2.1 release by @ekarabu in #669
• [RTL+VAL] I3C Version Update+FPGA Synth Fix for OTP by @ekarabu in #675
• [TB] Reduce caliptra FW images by @clayton8 in #680
• User/ekarabulut/fc strap fix by @ekarabu in #681
• Lowrisc zeroisation top level dv by @antmarzam in #668
• Expanded test cases for zeroisation by @marnovandermaas in #676
• [DOC] Minor editorial changes to fix OCP L.O.C.K. enable details by @calebofearth in #694
• [RTL] Update Rev i3c to tag v1p3 by @nileshbpat in #698
• [RTL+VAL] Fuse Map Update to Zeroized UDS and FE by @ekarabu in #696
• lock_test_fix by @ekarabu in #704
• Document AXI Streaming Boot by @tmichalak in #658
• [fuse_ctrl, tests] caliptra_ss_fuse_ctrl_test_zeroization_stuck_at by @andrea-caforio in #697
• [DOC] Caliptra ss zeroization integ update by @bharatpillilli in #705
• Update Release_Notes.md by @bharatpillilli in #706

Full Changelog: css-gen2-v1.0-rc2...css-gen2.1-v1.0-rc1

Caliptra Subsystem Gen 2.0 Release v1p0

Official Caliptra Subsystem Gen 2.0 Release v1p0

This release includes feedback on the release candidate from Caliptra Community.

Overview

Release for Caliptra Subsystem Gen 2.0 RTL, version 1p0. All features are frozen, verification plans are executed and signed-off, documentation has been updated, and CDC, Lint, RDC, Synthesis runs are clean.

Release Notes

What's Changed

• [VAL] Remove FIXMEs by @clayton8 in #415
• [DOC] Mention MCU MBOX SRAM accesses must be DWORD accesses by @clayton8 in #413
• [VAL] Test fixes for MCI Register Validation by @anjpar in #423
• [DOC] Spec clarifications by @clayton8 in #425
• [VAL] Fix randomization for mask select and SVA conditions by @upadhyayulakiran in #417
• [RTL] I3C Core rev update to tag v1p1 by @nileshbpat in #424
• [ENV] Kick off JTAG tests in parallel by @clayton8 in #434
• [DOC] Open test plan permissions; clarify SRAM requirement in spec by @calebofearth in #431
• [ENV] Remove submit JTAG script and add new JTAG TL by @clayton8 in #445
• [DOC] Fix issue Question regarding clock frequency #426 by @nileshbpat in #450
• [VAL] Add MCI cacheable test-case (not included in regr yet); tweak some C lib behavior by @calebofearth in #449
• [DOC] Add clarification on AXI DMA routes to SS HW spec by @calebofearth in #456
• [VAL] Minor fixes for MCI register tests by @anjpar in #460
• [DOC] Fix markdown syntax issue in HW spec by @calebofearth in #468
• [DOC] Add FIPS zeroization to generic input wires by @clayton8 in #473
• [DOC] Fix broken hyperlink in SS integration spec by @calebofearth in #469
• [DOC] Clarify AXI interconnect requirements in SS integration spec by @calebofearth in #477
• [fuse_ctrl, tools] Include pyyaml in requirements.txt by @andrea-caforio in #471
• [fuse_ctrl, test] Generate mmap header for testsuite by @andrea-caforio in #466
• GH Issue fixes by @nileshbpat in #480
• [TB] Coverage Dashboard Draft and test addition by @nileshbpat in #494
• Link update to coverage draft by @nileshbpat in #496
• User/ekarabulut/otp optional items by @ekarabu in #483
• [VAL][SVA] MCI Register test fixes and WDT Timer assertions fix by @anjpar in #497
• [TB] Add missing MCI coverage by @clayton8 in #500
• [SPEC] Update CSS memory map by @clayton8 in #522
• [Cov] Added Caliptra SS coverage updates by @nileshbpat in #526
• [RTL] Fix coverage miss bug due to missing parentheses by @anjpar in #529
• [RTL] Expose I3C SB signals for external I3C bypass boot, connect scan_mode to MCU, and spec updates by @clayton8 in #537
• [RTL] Fix MCU scan mode by @clayton8 in #553
• [DOC][VAL] Disconnect MCU ROM wr path in TB; clarify MCU ROM if connection req and SRAM error handling sections by @calebofearth in #550
• [DOC] Add Caliptra Core coverage analysis by @calebofearth in #543
• Coverage updates and fixed gh484 by @nileshbpat in #565
• [Cov] Coverage Doc Updates by @nileshbpat in #574
• [fuse_ctrl] Word-align fuse addresses by @andrea-caforio in #548
• [RTL] Expose RDC Related Signals 2.0 by @clayton8 in #580
• [VAL] Fix incorrect pointer in mci FW test by @anjpar in #573
• [BUG FIX] Drive a_data with zeroes for reads instead of wdata, which may be arbitrary by @calebofearth in #590
• pointed caliptra_v_2_0_1 branch by @ekarabu in #612
• [VAL] Update testbench to exercise SHA accelerator endian-swap feature in streaming mode by @calebofearth in #544
• [RTL] Update I3C Submodule and Add connections for cio_test* signals by @nileshbpat in #629

Full Changelog: css-gen2-v1.0-rc2...css-gen2-v1.0

Caliptra Subsystem Gen 2.0 Release v1p0-rc2

Overview

Release Candidate for Caliptra Subsystem Gen 2.0 RTL, version 1p0. All features are frozen, verification plans are executed and signed-off, documentation has been updated, and CDC, Lint, RDC, Synthesis runs are clean.

Release Notes

What's Changed

• Caliptra SS Integration Doc by @nileshbpat in #74
• Update MCI-error-agg diagram by @clayton8 in #75
• User/dev/ekarabulut/lcc fc spec 08 by @ekarabu in #78
• Ckuchta msft sram rmw by @clayton8 in #81
• updated int spec for FC and LCC by @ekarabu in #82
• Add MCI to Integration Spec by @clayton8 in #80
• Caliptra Subsystem Integration Specification Initial Version by @nileshbpat in #83
• access control table for fuse ctrl by @ekarabu in #87
• LCC different tokens for MANUF, PROD, END by @ekarabu in #89
• [fuse_ctrl, rtl] Use the latched AXI user id in the filter logic by @andrea-caforio in #93
• MCI ss spec update Debug and Interrupts by @clayton8 in #84
• Fuse Zeroization Flow with Transient State Handling by @ekarabu in #99
• MCI register cleanup + MCI DMI access + port renaming/cleanup for MCI by @clayton8 in #98
• [fuse_ctrl, integration] Fix fuse_ctrl background checks init error by @andrea-caforio in #90
• Ckuchta ss mci trace buffer by @clayton8 in #102
• PPD condition for SCRAP transition request by @ekarabu in #100
• Pateln streaming boot bringup by @nileshbpat in #107
• Resolved issue #106 by @nileshbpat in #108
• Ckuchta ss mci reg cleanup by @clayton8 in #110
• Qualification pipeline, VF Files, OS Headers, Build warnings fixes. by @nileshbpat in #86
• boot sequencer fsm fixed and added a write to SOC_MCI_REG_CPTRA_BOOT_GO by @nileshbpat in #112
• Fix SS_CONFIG_DON DMI, fix strobe access, and fix I3C-Core RDL in SS by @clayton8 in #113
• Removed unused defines and Fixed RTL Stub by @nileshbpat in #125
• UDS program with ROM by @ekarabu in #111
• MANUF DBG Flow with ROM execution by @ekarabu in #114
• Fuse controller Updates lowRISC by @ekarabu in #128
• Update to caliptra ss SoC Reg map by @nileshbpat in #130
• MCU MBOX protocol updates by @clayton8 in #132
• Update build flow to support per-test FW; update caliptra-rtl; fix some USER signals in top TB by @calebofearth in #140
• AXI manager spec update by @bharatpillilli in #143
• MCI Spec Updates for Debug, Straps, and Register Bank by @clayton8 in #139
• Nightly regression setup for Caliptra SubSystem by @anjpar in #152
• MCU Mbox SRAM Zeroization by @kedjenks in #151
• [RTL] AXI USER fixes and updates to mcu_cptra_bringup to execute FW UPD flow by @calebofearth in #150
• User/dev/ekarabulut/ss tb infra by @ekarabu in #162
• moved prim generic to ss_tb by @ekarabu in #153
• User/ekarabulut/fc update lowrisc 03 24 by @ekarabu in #172
• [3/25] Aggregate daily pull request by @calebofearth in #175
• [3/27] Aggregate daily pull request by @clayton8 in #196
• [3/28] Aggregate daily pull request by @clayton8 in #201
• [3/31] Aggregate daily pull request by @nileshbpat in #212
• [4/02] Aggregate daily pull request by @calebofearth in #229
• [04/03] Daily PR Merge by @nileshbpat in #239
• [4/04] Aggregate daily pull request by @calebofearth in #245
• [RTL][DOC] Update MCI RESET_RESON register and add HITLESS flows to spec by @clayton8 in #235
• [VAL][RTL] Add MCU Mbox Target User Test and Fix Bug#248 by @kedjenks in #249
• MCU JTAG system bus enabled and register access tests by @Nitsirks in #244
• [RDL, TB] Make MCI debug regs 32-bit; fix MCU SRAM exec testcase by @calebofearth in #246
• [fuse_ctrl, test] caliptra_ss_fuse_ctrl_external_clock by @andrea-caforio in #230
• [RTL][VAL] Fix Bug #258 and Add Invalid AXI and SRAM Address Test Cases by @kedjenks in #259
• LCC Tests by @nasahlpa in #260
• [fuse_ctrl, test] caliptra_ss_fuse_ctrl_bus_ecc_error by @andrea-caforio in #261
• [RTL] Connect MCU AXI signals AxCACHE, AxPROT, AxQOS, AxREGION to top-level by @calebofearth in #262
• [RTL][VAL] Add SOC BFM, MCU SRAM Exec Test, and AXI USER RO registers to MCI by @clayton8 in #263
• [VAL][RTL] MCU MBOX ECC Test and Update HW_STATUS to clear on lock by @kedjenks in #266
• [RTL, RDL, DOC] add aggregate error register connections at ss top by @Nitsirks in #271
• [RTL] Add RDC gated clocks and resets by @clayton8 in #279
• [RTL] Synthesis build fix (NVIDIA) by @calebofearth in #278
• [RTL][VAL] Add MCU Mbox Tests and Fix bug #280 by @kedjenks in #283
• [VAL] LCC related SVA and Cov by @ekarabu in #270
• [VAL] Add WDT smoke tests by @upadhyayulakiran in #284
• [RTL][VAL] Update MASK reg resets and add MCU SRAM debug mode test by @clayton8 in #286
• [RTL] clean lint for caliptra_ss_top by @Nitsirks in #288
• added prd test with fake ROM by @ekarabu in #218
• [TB] Enable native AXI interconnect data width conversion by @calebofearth in #273
• [fuse_ctrl, test] caliptra_ss_fuse_ctrl_init_fail by @andrea-caforio in #265
• fuse_ctrl coverage and assertions by @andrea-caforio in #276
• [fuse_ctrl, test] Randomize caliptra_ss_fuse_ctrl_axi_id by @andrea-caforio in #277
• [RTL][VAL] MCU TB Trace Testing + MCI interrupt fixes + MCI AXI miss response change by @clayton8 in #294
• [RTL], [VAL] JTAG Test for LCC and TB Cleaning by @ekarabu in #296
• MCTP Test, Fixes for I3C Reg rd wr test and more. by @nileshbpat in #237
• [fuse_ctrl, mmap] RMA token fix by @andrea-caforio in #302
• [lcc,tests] Adapt lcc_registers test by @nasahlpa in #303
• [lc_ctrl, test] caliptra_ss_lcc_clock_bypass by @andrea-caforio in #293
• [RTL][VAL] MCU Hitless Update Testcase and FIx for #299 by @kedjenks in #301
• [lcc, test] Extend caliptra_ss_jtag_lcc_st_trans by @nasahlpa in #305
• [fuse_ctrl, rtl] caliptra_ss alert trigger macros by @andrea-caforio in #289
• [lc_ctrl, test] caliptra_ss_lcc_alert by @andrea-caforio in #285
• [RTL] Expose RDC reset and clocks + Add FW EXEC DMI Reg in MCI by @clayton8 in https://github...

Caliptra Subsystem RTL v0.8

Overview

Preliminary release of Caliptra Subsystem RTL v0.8
v0.8 means features are frozen, ongoing validation and bug fixes are still anticipated.

Release Notes

https://github.com/chipsalliance/caliptra-ss/blob/2ec4914686d656467fae8ff40ee7da03ee6f5ec3/Release_Notes.md

What's Changed

• Initial commit of caliptra mcu by @Nitsirks in #1
• Spec updates by @Nitsirks in #2
• Caliptra SS Initial Release, Hello World, MCU + Caliptra IP by @nileshbpat in #15
• Add C Caliptra init test and cleanup directory structure by @calebofearth in #16
• [DOC] Add disclaimer to README clarifying subsystem status by @calebofearth in #17
• [TB] Add L0 regression file by @calebofearth in #18
• Pateln riscv upgrade 0923 by @nileshbpat in #20
• Caliptra 2p0 Subsystem specification by @nileshbpat in #22
• Added Sanity and DCCM access test by @nileshbpat in #21
• Updated Caliptra 0p5 SS spec by @bharatpillilli in #24
• [RTL] I3C Core instantiation and address map updates by @calebofearth in #23
• Updated firmware build to use soc_address_map by @calebofearth in #25
• Fix L0 regression by @calebofearth in #26
• Moved google docs content in markdown version (there are more pending but keeping it in md version for team to update) by @bharatpillilli in #27
• Fix compilespecs.yml by @calebofearth in #31
• Update caliptra-rtl to latest (0p8) by @calebofearth in #32
• integration of lc_ctrl's pkgs in caliptra-ss by @ekarabu in #38
• User/ekabulut/lc integ with axi by @ekarabu in #40
• added RMA strap and test case by @ekarabu in #43
• Ckuchta msft mci init by @clayton8 in #42
• changed alert interface by @ekarabu in #44
• TL-UL, Fuse_ctrl and lc_ctrl rebase onto OT's Earlgrey.PROD_M5 version by @anjpar in #46
• added compilation fixes by @ekarabu in #48
• Ckuchta msft mci wdt by @clayton8 in #45
• User/ekabulut/comp fix by @ekarabu in #51
• MCI & MCU spec update by @bharatpillilli in #50
• Update CaliptraSSHardwareSpecification.md - png link updates by @bharatpillilli in #52
• Update CaliptraSSHardwareSpecification.md - BootFSM pic, additional write up, MCU SRAM subsection update, MTIMER update by @bharatpillilli in #54
• Memory map redirection to integ spec statement by @bharatpillilli in #57
• Minor updates to CSSBootFSM by @clayton8 in #58
• instantiating mailboxes into mci by @Nitsirks in #53
• User/ekabulut/low risc fc 0115 by @ekarabu in #61
• User/ekabulut/mci lcc gasket by @ekarabu in #62
• Caliptra SS MCI Updates Plus plus by @nileshbpat in #60
• improved lcc gasket test by @ekarabu in #63
• mci lcc caliptra connections by @ekarabu in #64
• [RTL] Update MCU RISCV core version by @calebofearth in #59
• User/ekarabulut/lc fc test adjs by @ekarabu in #67
• Caliptra SS I3C integration by @nileshbpat in #66
• Updated submodule for caliptra-ss by @nileshbpat in #68
• Caliptra SS : Avery VIP YML File by @nileshbpat in #69
• Pateln i3c vip file by @nileshbpat in #70
• Caliptra Subsystem 0.8 Release by @nileshbpat in #73

New Contributors

• @Nitsirks made their first contribution in #1
• @nileshbpat made their first contribution in #15
• @calebofearth made their first contribution in #16
• @bharatpillilli made their first contribution in #24
• @ekarabu made their first contribution in #38
• @clayton8 made their first contribution in #42
• @anjpar made their first contribution in #46

Full Changelog: https://github.com/chipsalliance/caliptra-ss/commits/v0.8