[Enhancement] Integrate NVIDIA GEM for 5-40x Faster RTL Simulation in ChiselSim

[csbohan]

#GPU-Accelerated Simulation Backend: Integrate GEM for High-Performance RTL Simulation

Summary

I propose adding GEM (GPU-Accelerated Emulator-Inspired RTL Simulation) as an optional simulation backend for ChiselSim, enabling GPU-accelerated RTL simulation with 5-40x speedup over CPU-based simulators.

What is GEM?

GEM is an open-source RTL logic simulator developed by NVIDIA Research that leverages CUDA acceleration to dramatically speed up RTL simulation. Key characteristics:

• Performance: Delivers 5-40X speedup compared to leading CPU-based RTL simulators
• Architecture: Uses a virtual Very Long Instruction Word (VLIW) architecture optimized for CUDA execution
• Workflow: Similar to FPGA-based emulators - synthesizes designs to gate-level netlists, then maps to a virtual manycore Boolean processor for GPU execution
• Open Source: Available at https://github.com/NVlabs/GEM

Why This Would Be Valuable for ChiselSim

1. Significant Performance Gains

• Large Chisel designs can take hours or days to simulate on CPU
• GEM's GPU acceleration would enable faster design iteration and verification
• Particularly valuable for complex SoCs, processors, and large-scale designs

2. Cost-Effective Acceleration

• FPGA emulators are expensive and require specialized hardware
• GPUs are widely available in development environments and cloud platforms
• Makes high-performance simulation accessible to more developers

3. Complementary to Existing Backends

• Would be an optional backend alongside Treadle and Verilator
• Users could choose CPU-based simulation for debugging, GPU-based for performance
• Maintains ChiselSim's flexibility and modularity

4. Research and Education

• Enables faster exploration of design spaces
• Useful for academic research requiring extensive simulation
• Could accelerate Chisel-based design verification workflows

Proposed Integration Approach

1. Glue Layer: Create a ChiselSim backend that:

   • Converts Chisel-generated Verilog to GEM-compatible format
   • Handles the GEM synthesis and mapping pipeline
   • Manages VCD input/output for testbenches
   • Provides a clean API consistent with existing ChiselSim backends

2. Workflow Integration:

   • Leverage GEM's existing Yosys-based synthesis flow
   • Map Chisel designs through GEM's AIG transformation process
   • Support Chisel testbenches by converting to VCD format

3. Optional Dependency:

   • Make GEM backend optional (requires CUDA-capable GPU)
   • Graceful fallback to CPU backends if GPU unavailable
   • Clear documentation on requirements and setup

Technical Considerations

• Current Limitations: GEM requires non-interactive testbenches (static VCD inputs)
• Synthesis Overhead: One-time synthesis/mapping cost, but design can be simulated with multiple testbenches
• GPU Requirements: Requires CUDA-capable GPU (NVIDIA GPUs)
• Compatibility: Works with synchronous logic; async logic support is limited

Use Cases

• Large-scale processor verification
• SoC-level simulation
• Design space exploration requiring many simulation runs
• Regression testing with large test suites
• Academic research requiring extensive simulation

Questions for Discussion

1. Would the ChiselSim maintainers be interested in this integration?
2. What would be the preferred integration approach (plugin, optional backend, etc.)?
3. Are there specific ChiselSim APIs or interfaces we should follow?
4. Should this be a community contribution or maintained as a separate project?

References

• GEM GitHub: https://github.com/NVlabs/GEM
• GEM Paper: https://research.nvidia.com/publication/2025-06_gem-gpu-accelerated-emulator-inspired-rtl-simulation
• GEM Usage Docs: https://github.com/NVlabs/GEM/blob/main/usage.md

Next Steps

If there's interest, I'm happy to:

• Create a proof-of-concept implementation
• Contribute to the integration effort
• Help with documentation and testing

Looking forward to feedback and discussion!