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329 Open 774 Closed
329 Open 774 Closed
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Issues list

How to parse firrtl file/string to Circuit instance?
#4899 opened Apr 20, 2025 by canxin121
3
Inaccrate Infomation in the "Get me Verilog" section of FAQ
#4877 opened Apr 9, 2025 by scratch-er
4
Warnings occurs when using the VCS backend for simulation in SVSIM
#4848 opened Apr 1, 2025 by jcvclouds
[svsim][chiselsim] Support Questa
#4846 opened Mar 31, 2025 by seldridge
1
ChiselSim not allowing capturing of stdout/stderr
#4819 opened Mar 21, 2025 by seldridge
2
Chisel drops escaped % in printf if it is the last character in the format string and preceded by a space
#4818 opened Mar 21, 2025 by jackkoenig
Mux Tree Generation
#4809 opened Mar 18, 2025 by escou64
4
Bug in simulation verification
#4791 opened Mar 13, 2025 by tobias1012
3
Error When Connecting Analog-Only Bundle to Verilog Blackbox
#4775 opened Mar 6, 2025 by ysljung
AddDedupGroupAnnotations creates invalid Annotations w/ Definition argument
#4730 opened Feb 25, 2025 by seldridge
Provide ChiselEnum Value for OneHot encoding
#4729 opened Feb 25, 2025 by hellow554
Path of FixedIO's io generated invalid target
#4714 opened Feb 20, 2025 by dtzSiFive
1
Weird paths/Targets for Module Choices
#4713 opened Feb 20, 2025 by jackkoenig
Combine LTL assert-like intrinsic factories into a single trait
#4711 opened Feb 20, 2025 by fabianschuiki
@fabianschuiki
Update ScalaDoc of LTL AssertProperty and friends Documentation Only changing documentation
#4710 opened Feb 20, 2025 by fabianschuiki
@fabianschuiki
Enable Developer Certificate of Origin (DCO) for Chisel Repositories
#4705 opened Feb 18, 2025 by bensternthal
Stack Overflow when connecting Probe in FlatIO
#4687 opened Feb 13, 2025 by Emin017
1
BoringUtils: tapAndRead of literal throws error
#4663 opened Feb 4, 2025 by dtzSiFive
2
value emitVerilog is not a member of circt.stage.ChiselStage
#4603 opened Jan 9, 2025 by quantrpeter
1
Regarding the loss of active reset behavior of Reg or being overridden by RegInit.
#4567 opened Dec 18, 2024 by linmoIO
3
chisel3.util.Queue not working with SInt bug
#4536 opened Nov 27, 2024 by jiegec
1
3
Semantic Inconsistency in Intermediate FIRRTL File During Compilation: Incorrect reg Emission Instead of node and Loss of Memory readUnderWrite Behavior
#4526 opened Nov 25, 2024 by linmoIO
2
Initialize (FPGA) memory in Chisel 6
#4496 opened Nov 6, 2024 by schoeberl
1
Need for explicit widths in BlackBox parameters
#4488 opened Oct 26, 2024 by HakamAtassi
Selecting instances when using D/I and Class Property types crashes
#4476 opened Oct 16, 2024 by jackkoenig
1
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