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Description
Type of issue: Bug Report
Please provide the steps to reproduce the problem:
//> using repository https://central.sonatype.com/repository/maven-snapshots
//> using scala 2.13.16
//> using dep org.chipsalliance::chisel:7.0.0-RC3
//> using plugin org.chipsalliance:::chisel-plugin:7.0.0-RC3
//> using options -unchecked -deprecation -language:reflectiveCalls -feature -Xcheckinit
//> using options -Xfatal-warnings -Ywarn-dead-code -Ywarn-unused -Ymacro-annotations
import chisel3._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage
class Foo1 extends Module {
val a = IO(Input(Bool()))
val message = p"In $HierarchicalModuleName, a = $a"
assert(a, message)
printf(message)
}
object Main extends App {
println(
ChiselStage.emitSystemVerilog(
gen = new Foo1,
firtoolOpts = Array(
"--strip-debug-info",
"-disable-all-randomization",
"-default-layer-specialization=enable",
),
)
)
}What is the current behavior?
This emits:
module Foo1(
input clock,
reset,
a
);
`ifndef SYNTHESIS
always @(posedge clock) begin
if (~reset & ~a) begin
if (`ASSERT_VERBOSE_COND_)
$error("Assertion failed: In {{HierarchicalModuleName}}, a = %d\n", a);
if (`STOP_COND_)
$fatal;
end
if ((`PRINTF_COND_) & ~reset)
$fwrite(32'h80000002, "In %m, a = %d", a);
end // always @(posedge)
`endif // not def SYNTHESISWhat is the expected behavior?
{{HierarchicalModuleName}} should be %m.
Please tell us about your environment:
Other Information
What is the use case for changing the behavior?
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