Line up poke() and register output changes in .vcd trace #5107
Description
Type of issue: Feature Request
Is your feature request related to a problem? Please describe.
Today poke() signals are shown as changing on the falling edge.
I would like to see poke input signals immediately after the rising edge of the clock but before the waveform dump for that timestep occurs. This makes the .vcd dumps easier on the eye, because the change due to a peek/poke lines up with the change of a register.
Describe the solution you'd like
Showing poke() signals changing on the rising edge of a clock in Verilator dumps can be achieved in the generated C++ harness by inserting a poke/eval phase between the clock rise and the dump. The desired execution flow is:
clock = 0;
timeInc(1);
eval();
dump();
clock = 1;
timeInc(1);
eval(); // Logic settles on rising edge
// Pokes happen here
if (trace) {
// Re-evaluate to propagate pokes immediately
eval();
}
// changes from output of registers and poke() now appear on the rising edge
dump();