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Inaccrate Infomation in the "Get me Verilog" section of FAQ #4877
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Similar problems in the "Get me FIRRTL" section too. |
Good catch, yes this should be updated. This probably needs two things:
Anything related to If you have bandwidth for a PR, that would be great. Otherwise, I'll backlog this until I have time. |
I am a new Chisel user. I get confused by the inaccurate information in the docs when I am porting my Verilog design to Chisel. Eventually I realized the FAQ is not consistent with the behavior of the latest code, and I am posting an issue here. I do have free time to help improve the docs. However, since I am a new Chisel user, if I am writing the docs, it might contain inaccurate information and code that is not best practice. BTW, If I find some other problems in the docs, should I post a new issue or add these problems to this issue? |
We'll review it, so that's no problem. Sometimes it is also better if the docs are written by someone not tightly connected to the project. Whatever you want to do here is fine.
If you find new stuff, please open new issues. 👍 |
In the "Get me Verilog" section of the FAQ page (the links below), some information might be ambiguous, inaccurate, or outdated.
https://github.com/chipsalliance/chisel/blob/main/docs/src/resources/faqs.md#get-me-verilog
https://www.chisel-lang.org/docs/resources/faqs#get-me-verilog
The FAQ says that the following code generates a
HelloWorld.v
under PWD. However,emitSystemVerilog
returns a string, and it isemitSystemVerilogFile
that generates a file.The FAQ also suggests running the following command for fine control over verilog generation.
sbt 'runMain intro.HelloWorld --target-dir buildstuff --top-name HelloWorld'
However, the code spinet in the page does not contain an
intro.HelloWorld
object extendingApp
, so this command will fail. Some code like this is needed for the above command to work.The text was updated successfully, but these errors were encountered: