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Verilog: fix continuous assignments to variables #2492

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Verilog: fix continuous assignments to variables

Verilog: fix continuous assignments to variables #2492

Triggered via pull request September 24, 2024 20:27
@kroeningkroening
opened #731
continuous_assignment_to_variable_systemverilog3-fix
Status Failure
Total duration 13m 55s
Artifacts –

pull-request-checks.yaml

on: pull_request
check-ubuntu-20_04-make-clang
1m 16s
check-ubuntu-20_04-make-clang
check-ubuntu-20_04-make-gcc
55s
check-ubuntu-20_04-make-gcc
CentOS 8
1m 12s
CentOS 8
check-macos-14-make-clang
1m 11s
check-macos-14-make-clang
Emscripten build
1m 4s
Emscripten build
check-vs-2022-make-build-and-test
13m 41s
check-vs-2022-make-build-and-test
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3 errors
check-ubuntu-20_04-make-gcc
Process completed with exit code 2.
check-macos-14-make-clang
Process completed with exit code 2.
check-ubuntu-20_04-make-clang
Process completed with exit code 2.