Verilog: KNOWNBUG test for new

diffblue · Oct 31, 2024 · 48c423e · 48c423e
1 parent 6b0d346
commit 48c423e
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diff --git a/regression/verilog/class/new1.desc b/regression/verilog/class/new1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+new1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+The class is not yet recognized as a type.
diff --git a/regression/verilog/class/new1.sv b/regression/verilog/class/new1.sv
@@ -0,0 +1,6 @@
+class myClass;
+endclass
+
+module main;
+  myClass x = new;
+endmodule
diff --git a/src/hw_cbmc_irep_ids.h b/src/hw_cbmc_irep_ids.h
@@ -86,6 +86,7 @@ IREP_ID_ONE(verilog_implicit_typecast)
 IREP_ID_ONE(verilog_unique)
 IREP_ID_ONE(verilog_unique0)
 IREP_ID_ONE(verilog_priority)
+IREP_ID_ONE(verilog_new)
 IREP_ID_ONE(verilog_non_indexed_part_select)
 IREP_ID_ONE(verilog_indexed_part_select_plus)
 IREP_ID_ONE(verilog_indexed_part_select_minus)

diff --git a/src/verilog/parser.y b/src/verilog/parser.y
@@ -1447,6 +1447,11 @@ enum_name_declaration_list:
 class_scope: class_type TOK_COLONCOLON
 	;
 
+class_scope_opt:
+	  /* Optional */
+	| class_scope
+	;
+
 integer_type:
 	  integer_vector_type
 	| integer_atom_type
@@ -1863,6 +1868,12 @@ variable_decl_assignment:
 		{ $$ = $1; stack_expr($$).id(ID_declarator);
 		  addswap($$, ID_type, $2);
 		  addswap($$, ID_value, $4); }
+	| variable_identifier variable_dimension_brace '=' class_new
+	;
+
+class_new:
+	  TOK_NEW list_of_arguments_paren_opt
+		{ init($$, ID_verilog_new); mto($$, $2); }
 	;
 
 // System Verilog standard 1800-2017
@@ -3639,6 +3650,11 @@ list_of_arguments_paren:
 		{ $$ = $2; }
 	;
 
+list_of_arguments_paren_opt:
+	  /* Optional */
+	| list_of_arguments_paren
+	;
+
 list_of_arguments:
 	  /* Optional */
 		{ init($$); }