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Verilog: aval/bval lowering for casts to Bool
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This implements casing four-valued ava/bval encoded cast to Bool.  In
particular, values containing x or z cast to false, not true.
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kroening committed Oct 22, 2024
1 parent 01c39cf commit ef0c3c0
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Showing 7 changed files with 35 additions and 8 deletions.
8 changes: 3 additions & 5 deletions regression/verilog/SVA/sequence5.desc
Original file line number Diff line number Diff line change
@@ -1,14 +1,12 @@
KNOWNBUG
CORE
sequence5.sv
--bound 0
^\[main\.p0\] 1: PROVED up to bound 0$
^\[main\.p1\] 0: REFUTED$
^\[main\.p2\] 1'bx: PROVED up to bound 0$
^\[main\.p3\] 1'bz: PROVED up to bound 0$
^\[main\.p2\] 1'bx: REFUTED$
^\[main\.p3\] 1'bz: REFUTED$
^EXIT=10$
^SIGNAL=0$
--
^warning: ignoring
--
x and z are recognized as 'true', but 'true' is defined as a "nonzero known
value" (1800-2017 12.4).
2 changes: 1 addition & 1 deletion regression/verilog/SVA/sva_and1.desc
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Expand Up @@ -3,7 +3,7 @@ sva_and1.sv
--bound 0
^\[main\.p0\] always \(1 and 1\): PROVED up to bound 0$
^\[main\.p1\] always \(1 and 0\): REFUTED$
^\[main\.p2\] always \(1 and 32'b0000000000000000000000000000000x\): PROVED up to bound 0$
^\[main\.p2\] always \(1 and 32'b0000000000000000000000000000000x\): REFUTED$
^EXIT=10$
^SIGNAL=0$
--
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2 changes: 1 addition & 1 deletion regression/verilog/SVA/sva_iff1.desc
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ sva_iff1.sv
--bound 0
^\[main\.p0\] always \(1 iff 1\): PROVED up to bound 0$
^\[main\.p1\] always \(1 iff 0\): REFUTED$
^\[main\.p2\] always \(1 iff 32'b0000000000000000000000000000000x\): PROVED up to bound 0$
^\[main\.p2\] always \(1 iff 32'b0000000000000000000000000000000x\): REFUTED$
^EXIT=10$
^SIGNAL=0$
--
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2 changes: 1 addition & 1 deletion regression/verilog/SVA/sva_implies1.desc
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@ sva_implies1.sv
--bound 0
^\[main\.p0\] always \(1 implies 1\): PROVED up to bound 0$
^\[main\.p1\] always \(1 implies 0\): REFUTED$
^\[main\.p2\] always \(1 implies 32'b0000000000000000000000000000000x\): PROVED up to bound 0$
^\[main\.p2\] always \(1 implies 32'b0000000000000000000000000000000x\): REFUTED$
^EXIT=10$
^SIGNAL=0$
--
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17 changes: 17 additions & 0 deletions src/verilog/aval_bval_encoding.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,11 @@ bool is_four_valued(const typet &type)
return type.id() == ID_verilog_unsignedbv || type.id() == ID_verilog_signedbv;
}

bool is_four_valued(const exprt &expr)
{
return is_four_valued(expr.type());
}

bv_typet aval_bval_type(std::size_t width, irep_idt source_type)
{
PRECONDITION(!source_type.empty());
Expand Down Expand Up @@ -333,3 +338,15 @@ exprt aval_bval(const power_exprt &expr)
auto x = make_x(expr.type());
return if_exprt{has_xz, x, aval_bval_conversion(power_expr, x.type())};
}

exprt aval_bval(const typecast_exprt &expr)
{
// 'true' is defined as a "nonzero known value" (1800-2017 12.4).
PRECONDITION(is_aval_bval(expr.op()));
PRECONDITION(expr.type().id() == ID_bool);

auto op_has_xz = ::has_xz(expr.op());
auto op_aval = aval(expr.op());
auto op_aval_zero = to_bv_type(op_aval.type()).all_zeros_expr();
return and_exprt{not_exprt{op_has_xz}, notequal_exprt{op_aval, op_aval_zero}};
}
4 changes: 4 additions & 0 deletions src/verilog/aval_bval_encoding.h
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Expand Up @@ -24,7 +24,9 @@ Author: Daniel Kroening, [email protected]
// 1 1 | Z

bool is_four_valued(const typet &);
bool is_four_valued(const exprt &);
bool is_aval_bval(const typet &);
bool is_aval_bval(const exprt &);
std::size_t aval_bval_width(const typet &);
typet aval_bval_underlying(const typet &);

Expand All @@ -50,5 +52,7 @@ exprt aval_bval(const verilog_wildcard_equality_exprt &);
exprt aval_bval(const verilog_wildcard_inequality_exprt &);
/// lowering for **
exprt aval_bval(const power_exprt &);
/// lowering for typecasts
exprt aval_bval(const typecast_exprt &);

#endif
8 changes: 8 additions & 0 deletions src/verilog/verilog_synthesis.cpp
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Expand Up @@ -26,6 +26,7 @@ Author: Daniel Kroening, [email protected]
#include "verilog_typecheck_expr.h"

#include <cassert>
#include <iostream>
#include <map>
#include <set>

Expand Down Expand Up @@ -304,6 +305,13 @@ exprt verilog_synthesist::synth_expr(exprt expr, symbol_statet symbol_state)
}
else if(expr.id()==ID_typecast)
{
// When casting a four-valued scalar to bool,
// 'true' is defined as a "nonzero known value" (1800-2017 12.4).
if(is_aval_bval(to_typecast_expr(expr).op()) && expr.type().id() == ID_bool)
{
expr = aval_bval(to_typecast_expr(expr));
}
else
{
auto &op = to_typecast_expr(expr).op();

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