Verilog: add KNOWNBUG test for $low/$high

diffblue · Sep 24, 2024 · f2c1da9 · f2c1da9
1 parent 8d678b6
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diff --git a/regression/verilog/system-functions/low1.desc b/regression/verilog/system-functions/low1.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+low1.sv
+--module main --bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This yields an error in the typechecker.
diff --git a/regression/verilog/system-functions/low1.sv b/regression/verilog/system-functions/low1.sv
@@ -0,0 +1,13 @@
+module main;
+
+  logic [7:0] mask;
+
+  genvar i;
+  generate
+    for (i=$low(mask); i<=$high(mask); i = i + 1)
+      always_comb @* mask[i] = (i%2)==1;
+  endgenerate
+
+  assert final (mask == 'b10101010);
+
+endmodule