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Verilog: add tests for implicit nets #749

Merged
merged 1 commit into from
Oct 4, 2024
Merged

Verilog: add tests for implicit nets #749

merged 1 commit into from
Oct 4, 2024

Commits on Oct 4, 2024

  1. Verilog: add tests for implicit nets 

    SystemVerilog allows nets to be declared implicitly (1800 2017 Sec 6.10).
    @kroening
    kroening committed Oct 4, 2024
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