Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

SystemVerilog: extract typechecking for SVA #818

Merged
merged 1 commit into from
Nov 17, 2024
Merged

Conversation

kroening
Copy link
Member

@kroening kroening commented Nov 16, 2024

This moves the code for typechecking SVA expressions into separate methods
and into a separate file.

This moves the code for typechecking SVA expressions into separate methods
and into a separate file.
@kroening kroening marked this pull request as ready for review November 16, 2024 22:20
@tautschnig tautschnig merged commit 522b68e into main Nov 17, 2024
9 checks passed
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants