Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Verilog: add checks for operators that require integral types #825

Draft
wants to merge 1 commit into
base: main
Choose a base branch
from
Draft

Verilog: add checks for operators that require integral types #825

wants to merge 1 commit into from
+121 −22

Conversation

kroening
Copy link
Member

This adds checks to the typechecker to enforce that the operands have an integral type.

@kroening kroening force-pushed the must_be_integral branch 4 times, most recently from 374151c to 4a0e513 Compare November 17, 2024 20:39
@kroening
Verilog: add checks for operators that require integral types
f56d64e 
This adds checks to the typechecker to enforce that the operands have an
integral type.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
Verilog
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
1 participant
@kroening