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modules/zstd: Rework ZSTD Decoder#1654

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lpawelcz wants to merge 42 commits intogoogle:maingoogle/xls:mainfrom antmicro:zstd_decoderantmicro/xls:zstd_decoderCopy head branch name to clipboard

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• modules/zstd/cocotb: Add cocotb testing utilities

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• modules/zstd/memory/MemReader: Add cocotb tests

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• modules/zstd/memory/AxiWriter: Add cocotb test

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• modules/zstd/memory/MemWriter: Add cocotb test

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• modules/zstd/memory/README: Describe verilog simulation

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• CI/modules-zstd: Add calls to verilog simulation targets

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• modules/zstd/BUILD: increase pipeline_stages for DecoderMux proc

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• xls/modules/zstd: expose fifo verilog module

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• modules/rle/common: Add RLE output struct

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• modules/zstd: Remove MagicNumberDecoder

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• modules/zstd: Remove BlockDecoder proc

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• modules/zstd: Remove DecDemux proc

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• modules/zstd/block_header: Specify new type for the block size

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• modules/zstd: Cleanup BlockHeader

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• modules/zstd/BUILD: Introduce common codegen args

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• modules/zstd: Add AxiCsrAccessor

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• modules/zstd: Add CsrConfig

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• modules/zstd: Add FrameHeaderDecoder

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• modules/zstd: Add BlockHeaderDecoder

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• modules/zstd: Add RawBlockDecoder

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• modules/zstd: Add RleBlockDecoder

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• modules/zstd: Add ZstdDecoder

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• modules/zstd/cocotb: Add ZSTD frame generator library

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• dependency_support: Add zstandard python library

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• modules/zstd: Add verilog simulation of the ZstdDecoder

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• modules/zstd: Update documentation

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• modules/zstd: Add AxiRamReader implementation

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• modules/zstd/zstd_dec: Add DSLX tests for ZstdDecoder

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• modules/zstd/zstd_dec: handle contents of the Status CSR

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• modules/zstd/data_generator: fix formatting

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• modules/zstd/memory:axi_stream_remove_empty: Fix byte ordering

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• modules/zstd/memory/axi_stream_remove_empty: Extract remove_empty_bytes function into a separate proc

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• modules/zstd/memory/axi_writer: Assign parameterized max lane value

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• modules/zstd/memory/mem_writer: Add support for not-full input data packets

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• modules/zstd/memory/mem_writer: Add MemWriterInternal proc

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• modules/zstd/zstd_dec: Write decoded data to the memory

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• modules/zstd/zstd_dec: Remove stream-based output interface

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• modules/zstd/zstd_dec_cocotb_test: Improve Verilog simulation

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• modules/zstd/README: Update output interface description

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• modules/zstd/memory/axi_stream_remove_empty: add fifo module definition for verilog library

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• [TEMP] modules/zstd/memory/mem_writer: Reduce the amount of random test cases

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• modules/zstd/zstd_dec: use regular cast instead of checked_cast on status enums

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