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Fix: async spi write returns before tx finishing #34

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merged 3 commits into from
Sep 28, 2024
Merged

Fix: async spi write returns before tx finishing #34

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7864875
refactor(uart): refine fn arg order
andelf Sep 28, 2024
1426f81
wip(spi): add async irq done wait
andelf Sep 28, 2024
a6e2dfc
fix(spi): add busy loop waiting for tx finish
andelf Sep 28, 2024
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70 changes: 36 additions & 34 deletions src/spi/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -9,16 +9,17 @@ use core::marker::PhantomData;
use core::ptr;

use embassy_futures::join::join;
use embassy_futures::yield_now;
use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
// re-export
pub use embedded_hal::spi::{Mode, MODE_0, MODE_1, MODE_2, MODE_3};
pub use hpm_metapac::spi::vals::{AddrLen, AddrPhaseFormat, DataPhaseFormat, TransMode};

use self::consts::*;
use crate::dma::{self, word, ChannelAndRequest};
use crate::gpio::AnyPin;
use crate::mode::{Async, Blocking, Mode as PeriMode};
pub use crate::pac::spi::vals::{AddrLen, AddrPhaseFormat, DataPhaseFormat, TransMode};
use crate::time::Hertz;

#[cfg(any(hpm53, hpm68, hpm6e))]
Expand All @@ -32,8 +33,9 @@ mod consts {
pub const FIFO_SIZE: usize = 4;
}

// ==========
// Helper enums
// NOTE: SPI end interrupt is not working under DMA mode

// - MARK: Helper enums

/// Time between CS active and SCLK edge.
#[derive(Copy, Clone)]
Expand Down Expand Up @@ -100,8 +102,7 @@ impl Into<u8> for CsHighTime {
}
}

// ==========
// Config
// - MARK: Config

#[derive(Clone, Copy)]
pub struct Timings {
Expand Down Expand Up @@ -200,8 +201,7 @@ pub enum Error {
FifoFull,
}

// ==========
// SPI driver
// - MARK: SPI driver

/// SPI driver.
#[allow(unused)]
Expand Down Expand Up @@ -351,9 +351,11 @@ impl<'d> Spi<'d, Blocking> {
d2.set_as_alt(d2.alt_num());
d3.set_as_alt(d3.alt_num());

let cs_index = cs.cs_index();
#[cfg(ip_feature_spi_cs_select)]
T::info().regs.ctrl().modify(|w| w.set_cs_en(cs_index));
{
let cs_index = cs.cs_index();
T::info().regs.ctrl().modify(|w| w.set_cs_en(cs_index));
}

Self::new_inner(
peri,
Expand Down Expand Up @@ -500,6 +502,7 @@ impl<'d> Spi<'d, Async> {
let r = self.info.regs;

self.set_word_size(W::CONFIG);

self.configure_transfer(data.len(), 0, &TransferConfig::default())?;

r.ctrl().modify(|w| w.set_txdmaen(true));
Expand All @@ -513,8 +516,11 @@ impl<'d> Spi<'d, Async> {

r.ctrl().modify(|w| w.set_txdmaen(false));

// TODO: should wait tx done via INTRST
// In embassy-stm32 this is a busy wait
// NOTE: SPI end(finish) interrupt is not working under DMA mode, a busy-loop wait is necessary for TX mode.
// The same goes for `transfer` fn.
while r.status().read().spiactive() {
yield_now().await;
}

Ok(())
}
Expand Down Expand Up @@ -578,6 +584,11 @@ impl<'d> Spi<'d, Async> {
w.set_txdmaen(false);
});

// See `write`
while r.status().read().spiactive() {
yield_now().await;
}

Ok(())
}

Expand Down Expand Up @@ -627,6 +638,7 @@ impl<'d, M: PeriMode> Spi<'d, M> {
};

this.enable_and_configure(&config).unwrap();

this
}

Expand Down Expand Up @@ -797,6 +809,10 @@ impl<'d, M: PeriMode> Spi<'d, M> {

// In blocking mode, the final speed is not faster than normal mode
pub fn blocking_datamerge_write(&mut self, data: &[u8], config: &TransferConfig) -> Result<(), Error> {
if data.is_empty() {
return Ok(());
}

let r = self.info.regs;

flush_rx_fifo(r);
Expand Down Expand Up @@ -831,6 +847,10 @@ impl<'d, M: PeriMode> Spi<'d, M> {

// Write in master mode
pub fn blocking_write<W: Word>(&mut self, data: &[W]) -> Result<(), Error> {
if data.is_empty() {
return Ok(());
}

let r = self.info.regs;
let config = TransferConfig::default();

Expand All @@ -852,6 +872,10 @@ impl<'d, M: PeriMode> Spi<'d, M> {
}

pub fn blocking_read<W: Word>(&mut self, data: &mut [W]) -> Result<(), Error> {
if data.is_empty() {
return Ok(());
}

let r = self.info.regs;
let mut config = TransferConfig::default();
config.transfer_mode = TransMode::READ_ONLY;
Expand Down Expand Up @@ -939,36 +963,14 @@ impl<'d, M: PeriMode> Spi<'d, M> {
}

// ==========
// Helper functions
// - MARK: Helper types and functions

fn flush_rx_fifo(r: crate::pac::spi::Spi) {
while !r.status().read().rxempty() {
let _ = r.data().read();
}
}

// ==========
// Interrupt handler

/// SPI Interrupt handler.
pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}

impl<T: Instance> crate::interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
on_interrupt(T::info().regs, T::state())
}
}

unsafe fn on_interrupt(r: crate::pac::spi::Spi, s: &'static State) {
let _ = (r, s);
todo!()
}

// ==========
// Helper types and functions

struct State {
#[allow(unused)]
waker: AtomicWaker,
Expand Down
6 changes: 3 additions & 3 deletions src/uart/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -495,9 +495,9 @@ impl<'d> UartRx<'d, Async> {
/// Create a new rx-only UART with a request-to-send pin
pub fn new_with_rts<T: Instance>(
peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
config: Config,
) -> Result<Self, ConfigError> {
Expand Down Expand Up @@ -837,9 +837,9 @@ impl<'d> Uart<'d, Async> {
peri: impl Peripheral<P = T> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
config: Config,
Expand Down Expand Up @@ -871,8 +871,8 @@ impl<'d> Uart<'d, Async> {
peri: impl Peripheral<P = T> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
de: impl Peripheral<P = impl DePin<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
tx_dma: impl Peripheral<P = impl TxDma<T>> + 'd,
rx_dma: impl Peripheral<P = impl RxDma<T>> + 'd,
config: Config,
Expand Down
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