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[hw,mbx] Sync mailbox from integrated_dev to master #24437

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@Razer6 Razer6 commented Aug 29, 2024

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@Razer6 Razer6 requested a review from a team as a code owner August 29, 2024 14:13
@Razer6 Razer6 requested review from hcallahan-lowrisc and removed request for a team August 29, 2024 14:13
@Razer6 Razer6 force-pushed the mbx-sync-to-master branch 3 times, most recently from 7bd9358 to acb3ff8 Compare August 29, 2024 14:37
@Razer6 Razer6 force-pushed the mbx-sync-to-master branch 2 times, most recently from 90bb902 to c31c8b7 Compare September 24, 2024 14:31
Razer6 and others added 19 commits September 26, 2024 15:42
Signed-off-by: Robert Schilling <[email protected]>
Signed-off-by: Robert Schilling <[email protected]>
Signed-off-by: Robert Schilling <[email protected]>
Razer6 and others added 25 commits September 26, 2024 15:42
Minor fixes to support use of vcs as an alternative.

Signed-off-by: Adrian Lees <[email protected]>
Clearing of Abort condition resets both inbound and outbound
traffic, clears down the count of outstanding requests and
suppresses any subsequent core-side TL-UL read responses.
Since the Abort request clears Ready, keep the Read Data
register zeroed until the abort is acknowledged.

Signed-off-by: Adrian Lees <[email protected]>
Abort acknowledgement is of the highest priority, permitting
its use as a FW-driven reset mechanism even if there was no
explicit SoC-side Abort request.

Signed-off-by: Adrian Lees <[email protected]>
Abort clearing/FW-initiated reset must clear the count
of outstanding requests to suppress delayed responses from
propagating into the mailbox logic.

Signed-off-by: Adrian Lees <[email protected]>
This ensures that all existing tests are mapped to a testpoint.

Signed-off-by: Andreas Kurth <[email protected]>
Instead of only using the next state signal of the FSM, we also take into
account the current state, to compute the transition edge into the Read
and Abort state, that generates the event for the IRQ primitive.

Closes lowRISC/opentitan-integrated#714

Signed-off-by: Robert Schilling <[email protected]>
Modify documentation to specify that the mailbox
limit addresses are inclusive and indicate the final
usable DWORD location.
Update DIF address checks accordingly.

Signed-off-by: Adrian Lees <[email protected]>
Migrate code from smoke sequence into base sequence to
form the basis of a test suite include stress sequences.
Minor corrections. No significant impact upon current
smoke sequence.

Signed-off-by: Adrian Lees <[email protected]>
Introduce constrained, randomized sequence item that
describes a request and response communication.
Multiple back-to-back transactions between IP block resets.
Multiple iterations, separated by IP block resets.

Signed-off-by: Adrian Lees <[email protected]>
Simple stress test runs more iterations of more
transactions. To be extended.

Signed-off-by: Adrian Lees <[email protected]>
Generate SoC-side Aborts, Core-side Errors and Core-Side
FW-initiated resets (Abort acknowledgements).
Support interrupt-driven or CSR-driven operation.

Signed-off-by: Adrian Lees <[email protected]>
Co-authored-by: Harry Callahan <[email protected]>
Randomization of TL-UL access and response timings
within stress sequence(s).
Introduce 'zero delays' stress sequence for throughput
testing and exercising back-pressuring logic.

Signed-off-by: Adrian Lees <[email protected]>
The former is a test specifically written for Mailbox (and it already
exists) while the latter is a generic test that combines tests
specifically written for Mailbox.  Both should be part of V2 (in
contrast to the generic `stress_all_with_rand_reset`, which is part of
V3).

Signed-off-by: Andreas Kurth <[email protected]>
A mailbox con either be a PCIe mailbox or a FW mailbox. In case of the
PCIe setting, the SOC reagisters 0x0 and 0x4 implement the capability
header functionality, but this is done outside of the mbx RTL. PCIe
mailboxes do not use the SOC_INTR_DATA/ADDR registers. FW-based
mailboxes on the other hand only use the SOC_INTR_DATA/ADDR registers
but no capability headers. Previously, it was decided to alias both
registers as they are used orthogonally. However, this deceission was
revised.

This PR moves the SOC_INTR_DATA/ADDR registers to the end of the SOC
register interface to not alias with any capability header registers
for PCIe mailboxes

Signed-off-by: Robert Schilling <[email protected]>
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Reviewed with the PR branch at dace55d

I've just been looking at this today, and it seems that some commits have been squashed together as part of the migration. For example, 0a2ca18 appears to have been squashed into 978e5c5 to create 382a08a, as well as some other changes at the same time. Was this intentional? It's making the reviewing process tricky, as it's harder to see any new or unintended changes made as part of the migration. I can probably power through if it would be too difficult to go backwards now, but it's going to take me longer to work through.
The script I'm using to try and simplify the review process is telling me the following:

Number of commits touching hw/ip/mbx in original branch : 86
Number of commits in migration branch (PR) : 73
WARNING: the following 15 commits may not have been migrated:
Lost commit : 0a2ca184b210 [hw,rtl,mbx] System register interface implementation
Lost commit : 240988180280 [hw,mbx,rtl] Implement DOE IRQ support
Lost commit : 6cfc94ea41e4 [hw,mbx,rtl] Use Mubi-regwen for range config
Lost commit : 68c211772acb [hw,mbx,rtl] Remove Async message support registers
Lost commit : aed591a6a0bf [hw,mbx,rtl] Remove hostif.status.ready register
Lost commit : 61b9d6fd5f23 [mbx] Rename SoC-facing port to `soc`
Lost commit : 3cc3af9c49c3 [hw,mbx,rtl] Move error bit from HOST.STATUS to HOST.CONTROL
Lost commit : 424e50afe822 [hw,mbx,rtl] More concise register definition
Lost commit : a81183fa5e3e [hw,mbx,rtl] Rename DOE IRQ signals on host side
Lost commit : 664199cd6dc7 [hw,mbx,rtl] Busy is fully hardware controlled
Lost commit : 354ea3b1fd6d [hw,mbx,rtl] Fix permissions on CORE.STATUS and SOC.CONTROL
Lost commit : 6d22e32b9a8d [mbx] Stable Ready bit required in ombx assertion
Lost commit : 7d2a40351e9d [hw,mbx,rtl] Add CSR registers for asynchronous message support
Lost commit : 6557ab1c9ff7 [hw,mbx,rtl] Add top-level strap for async message support
Lost commit : bb2f84a3b6c6 [hw,mbx,rtl] Add an error IRQ to notify host
WARNING: the following 2 commits may have been added:
Added commit : 87b2faeff6d9 [hw,mbx] Update source files with new license header
Added commit : dace55df6457 [hw,mbx] Update bazel rules for generating C/Rust headers

Quite a few of the 'lost' commits appear to have been squashed into their neighbors.
Thanks

@Razer6
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Razer6 commented Sep 27, 2024

That is strange. No that is not intentional. Let, me try that again and see if I get a different list of commits.

@Razer6
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Razer6 commented Sep 27, 2024

@hcallahan-lowrisc Not sure what happened here. They are indeed lost and squashed. I re-created the PR with all commits in #24687

@Razer6 Razer6 closed this Sep 27, 2024
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6 participants