[hw,mbx] Sync mailbox from integrated_dev to master #24687
Commits on Sep 27, 2024
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[hw,mbx,rtl] RTL skeleton for DOE Mailbox
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Implementation of the host interface
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Added IRQ primitive
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Rename set/clear signals for better meaning
Signed-off-by: Robert Schilling <[email protected]>
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[hw,rtl,mbx] System register interface implementation
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] External control register
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Implement DOE IRQ support
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] FW2FW IRQ registers
Signed-off-by: Robert Schilling <[email protected]>
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[mbx,doc] Initial ingestion of mailbox spec
Signed-off-by: Neeraj Upasani <[email protected]>
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[hw,mbx,rtl] Add countermeasure testplan
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Implement SRAM arbiter
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Inbound mailbox implementation
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Simplify and fix signal assignments
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Refactor top-level signalling and naming
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Adaptions to the signaling
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Use Mubi-regwen for range config
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] No IRQ muxing between ready and abort
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Make DOE Interrupt Addr/Data an alias to host interface
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Recoverable alert on invalid memory access
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Remove Async message support registers
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Remove hostif.status.ready register
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Outbound mailbox implementation
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Clarifications to the ombx signalling
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Let the ombx create the DOE interrupt
Signed-off-by: Robert Schilling <[email protected]>
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[mbx] Rename OT-facing port to
coreThis is in-line with our conventions. Signed-off-by: Andreas Kurth <[email protected]>
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[mbx] Rename SoC-facing port to
socThis is hopefully less ambiguous to OT devs than `sys`. Signed-off-by: Andreas Kurth <[email protected]>
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[mbx/rtl] Fix signal names of TL-UL
sramportsSigned-off-by: Andreas Kurth <[email protected]>
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[mbx/rtl] Add missing reg WE onehot check assertion
Signed-off-by: Andreas Kurth <[email protected]>
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[mbx/rtl] Add missing connections to/from
mbx_soc_reg_topSigned-off-by: Andreas Kurth <[email protected]>
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[hw,mbx,rtl] Move error bit from HOST.STATUS to HOST.CONTROL
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Invalid range config sets busy
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Make registers explicitly read-only in hardware
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] More concise register definition
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Rename DOE IRQ signals on host side
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Raise a system IRQ if host raises an error
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Busy is fully hardware controlled
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Fix permissions on CORE.STATUS and SOC.CONTROL
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Add mbx to makefile and fix comment
Signed-off-by: Robert Schilling <[email protected]>
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[mbx/rtl] Comment broken assertions out
All these assertions include at least one undefined signal. We don't have time to fix them right now; this is tracked in issue lowRISC/opentitan-integrated#476. Signed-off-by: Andreas Kurth <[email protected]>
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[mbx] Exclude most CSRs from automated tests
Many of Mailbox's CSRs have side effects or are implemented by a hardware mechanism that automated CSR tests are not aware of. For this reason, those CSRs have to be (partially) excluded from automated tests. To enable progress, at the moment probably too many exclusions are in place, though. This should be revisited, which is tracked in issue lowRISC/opentitan-integrated#477 and by the TODO comments in this commit. Signed-off-by: Andreas Kurth <[email protected]>
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Signed-off-by: Andreas Kurth <[email protected]>
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[hw,mbx,rtl] Fix undriven signals and busy clear
This PR fixes two issues: * It connects drives sysif_status_ready_i * It clears the busy signal if the memory range becomes valid Signed-off-by: Robert Schilling <[email protected]>
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[mbx] Advance pointer on initial write
Ensure that write pointer advances on initial word of a request message even when bus access is granted immediately, to prevent overwriting of the first message word. Signed-off-by: Adrian Lees <[email protected]>
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[hw,mbx,rtl] Fix linting errors on mailbox
Signed-off-by: Robert Schilling <[email protected]>
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[mbox/lint] Fix a concatenation error
This should be a replication and not a concatenation operation. Signed-off-by: Michael Schaffner <[email protected]>
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Signed-off-by: Michael Schaffner <[email protected]>
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[mbx] Stable Ready bit required in ombx assertion
Outbox assertion requires the current state of Ready bit at all times, not just the transition to Ready. Signed-off-by: Adrian Lees <[email protected]>
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Correct a couple of incorrect assertions to allow smoke test to pass. Ensure that the read/write ptr assertions validate increment. Introduce a new assertion to catch Ready IRQ overtaking write traffic (disabled for now, tracking in lowRISC/opentitan-integrated#476). Minor whitespace tweaks. Signed-off-by: Adrian Lees <[email protected]>
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[mbx, dv] - First pass mbx ip dv enviorment and smoke test
Includes mbx tb along with env, seq_lib and mbx_sim_cfg.hjson First pass smoke test with Mailbox data exchance Basic Self-checking enabled Pending, abort and interrup content. Signed-off-by: Kevin Virgen <[email protected]> Signed-off-by: Harry Callahan <[email protected]>
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[dv,darjeeling] Include DMA and MBX smoke tests in CI
DMA and MBX smoke tests are passing; incorporate them into Darjeeling DV smoke runs. Introduce `mbx_common_vseq` required for common tests. Signed-off-by: Adrian Lees <[email protected]>
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[mbx,dv] Dv tweaks to get csr tests running in the smoke regression
Signed-off-by: Harry Callahan <[email protected]>
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[hw,mbx,rtl] Defer IRQ generation until write response received
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx] Make lint clean for unused signal
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Gate all valid received with current request
This allows the hardware to capture the current in flight request, which is not yett counted Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Use the transition to Read or to Abort state to generate…
… IRQ The state transition generates a single event that is used byt the IRQ primitive to generate a leveled interrupt, that can be cleared by software. Closes lowRISC/opentitan-integrated#647 Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Initialize the outbound read ptr when range becomes valid
Signed-off-by: Robert Schilling <[email protected]>
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[mbx] Correct assertion and updating of OUTBOUND_OBJECT_SIZE
Decrement object size on every valid TL-UL transaction, not just those which are immediately accepted. Modify assertion to check SRAM read address only when it has been loaded and is about to be used. Signed-off-by: Adrian Lees <[email protected]>
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[hw,mbx,rtl] Add CSR registers for asynchronous message support
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Add top-level strap for async message support
Needed for the external cap header implementation Signed-off-by: Robert Schilling <[email protected]>
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[mbx, dv] Refactor tb interrupt functionality
- Provides virtual interfaces for both core side and soc side interrupts - `wait_for_core_interrupt` now only looks at the core_ready interrupt and includes a clock based timeout and sensible error messages - Added `wait_for_soc_interrupt` to wait for soc side interrupt Signed-off-by: Greg Chadwick <[email protected]>
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[mbx,dv] Add IRQ usage to mailbox smoke
This also disables interrupt checks in the scoreboard as they currently do not function correctly. Signed-off-by: Greg Chadwick <[email protected]>
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[hw,mbx,rtl] Trigger an error for out-of-bounds imbx write
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Add an error IRQ to notify host
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,dv] Add new interrupt to the DV environment
Signed-off-by: Robert Schilling <[email protected]>
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[dv,mbx] Changes for vcs support
Minor fixes to support use of vcs as an alternative. Signed-off-by: Adrian Lees <[email protected]>
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[mbx] Fault recovery via Abort mechanism
Clearing of Abort condition resets both inbound and outbound traffic, clears down the count of outstanding requests and suppresses any subsequent core-side TL-UL read responses. Since the Abort request clears Ready, keep the Read Data register zeroed until the abort is acknowledged. Signed-off-by: Adrian Lees <[email protected]>
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[mbx] Abort acknowledgement always resets FSMs.
Abort acknowledgement is of the highest priority, permitting its use as a FW-driven reset mechanism even if there was no explicit SoC-side Abort request. Signed-off-by: Adrian Lees <[email protected]>
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[mbx] Reset request count when abort cleared.
Abort clearing/FW-initiated reset must clear the count of outstanding requests to suppress delayed responses from propagating into the mailbox logic. Signed-off-by: Adrian Lees <[email protected]>
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[mbx/dv] Create scaffold for testplan
This ensures that all existing tests are mapped to a testpoint. Signed-off-by: Andreas Kurth <[email protected]>
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[hw,mbx,rtl] Use the transition to the Read/Abort to generate the IRQ
Instead of only using the next state signal of the FSM, we also take into account the current state, to compute the transition edge into the Read and Abort state, that generates the event for the IRQ primitive. Closes lowRISC/opentitan-integrated#714 Signed-off-by: Robert Schilling <[email protected]>
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[mbx] Limit addresses are inclusive
Modify documentation to specify that the mailbox limit addresses are inclusive and indicate the final usable DWORD location. Update DIF address checks accordingly. Signed-off-by: Adrian Lees <[email protected]>
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[dv,mbx] Tidying, restructuring and minor fixes.
Migrate code from smoke sequence into base sequence to form the basis of a test suite include stress sequences. Minor corrections. No significant impact upon current smoke sequence. Signed-off-by: Adrian Lees <[email protected]>
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[dv,mbx] Extended smoke sequence
Introduce constrained, randomized sequence item that describes a request and response communication. Multiple back-to-back transactions between IP block resets. Multiple iterations, separated by IP block resets. Signed-off-by: Adrian Lees <[email protected]>
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[dv,mbx] Placeholder stress sequence.
Simple stress test runs more iterations of more transactions. To be extended. Signed-off-by: Adrian Lees <[email protected]>
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[dv,mbx] Extended stress testing
Generate SoC-side Aborts, Core-side Errors and Core-Side FW-initiated resets (Abort acknowledgements). Support interrupt-driven or CSR-driven operation. Signed-off-by: Adrian Lees <[email protected]> Co-authored-by: Harry Callahan <[email protected]>
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[dv,mbx] Vary TL-UL access/response timings.
Randomization of TL-UL access and response timings within stress sequence(s). Introduce 'zero delays' stress sequence for throughput testing and exercising back-pressuring logic. Signed-off-by: Adrian Lees <[email protected]>
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[dv,mbx] Reduce num_iters/num_txns for mbx_stress to avoid timeouts
Signed-off-by: Harry Callahan <[email protected]>
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[mbx,dv] Test hw mechanism for reporting imbx oob
Signed-off-by: Harry Callahan <[email protected]>
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[hw,mbx,rtl] Gate the AsyncMsg support with feature strap and enable
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] No direct prim_generic_flop instances
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,rtl] Clear interrupts when acknowledging an abort
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx,dv] Disable not implemented stress tests
Signed-off-by: Robert Schilling <[email protected]>
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[mbx/dv] Separate
mbx_stressfrommbx_stress_allin testplanThe former is a test specifically written for Mailbox (and it already exists) while the latter is a generic test that combines tests specifically written for Mailbox. Both should be part of V2 (in contrast to the generic `stress_all_with_rand_reset`, which is part of V3). Signed-off-by: Andreas Kurth <[email protected]>
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[mbx/dv] Add
mbx_stress_zero_delaystest tombx_stresstest pointSigned-off-by: Andreas Kurth <[email protected]>
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[mbx/dv] Add test point for out-of-bound inbound mailbox accesses
Signed-off-by: Andreas Kurth <[email protected]>
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[hw,mbx,rtl] Move SOC_INTR_ADDR/DATA registers to the end
A mailbox con either be a PCIe mailbox or a FW mailbox. In case of the PCIe setting, the SOC reagisters 0x0 and 0x4 implement the capability header functionality, but this is done outside of the mbx RTL. PCIe mailboxes do not use the SOC_INTR_DATA/ADDR registers. FW-based mailboxes on the other hand only use the SOC_INTR_DATA/ADDR registers but no capability headers. Previously, it was decided to alias both registers as they are used orthogonally. However, this deceission was revised. This PR moves the SOC_INTR_DATA/ADDR registers to the end of the SOC register interface to not alias with any capability header registers for PCIe mailboxes Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx] Update source files with new license header
Signed-off-by: Robert Schilling <[email protected]>
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[hw,mbx] Update bazel rules for generating C/Rust headers
Signed-off-by: Robert Schilling <[email protected]>
