Make PLIC interrupt 0 (no interrupt) more robust #28776
Open
+48
−24
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In PLIC, interrupt ID 0 is special - it is reserved for "no interrupt". The way this is implemented in
rv_plicis by simply asking nicely for integrators to tie the interrupt ID 0 input to 0.This is suboptimal because it allows integration mistakes, and there is a dangerous
assumefor FPV - this is directly added insiderv_plic.sv. Unless there's some flow magic to convert this to anassert(I didn't see anything) then this can cause nonsensical formal results if you accidentally violate that assumption.This changes that assume to an assert so it is at least checked. I would have liked to remove the pin entirely so there is no chance of making that mistake, but that is a much bigger change that requires changing the external interface.