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Make PLIC interrupt 0 (no interrupt) more robust #28776

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3 changes: 3 additions & 0 deletions hw/ip_templates/rv_plic/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,9 @@ The RV_PLIC module is designed to manage various interrupt sources from the
peripherals. It receives interrupt events as either edge or level of the
incoming interrupt signals (``intr_src_i``) and can notify multiple targets.

Note that the lowest bit of ``intr_src_i`` is must be tied to 0 because it corresponds interrupt ID 0 which is reserved to mean "no interrupt". This is
verified with an assertion inside `rv_plic`.

## Compatibility

The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification.
2 changes: 1 addition & 1 deletion hw/ip_templates/rv_plic/data/rv_plic.hjson.tpl
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Expand Up @@ -54,7 +54,7 @@

param_list: [
{ name: "NumSrc",
desc: "Number of interrupt sources",
desc: "Number of interrupt sources (including the 'no interrupt' ID 0)",
type: "int",
default: "${src}",
local: "true"
Expand Down
5 changes: 3 additions & 2 deletions hw/ip_templates/rv_plic/fpv/tb/rv_plic_tb.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ module ${module_instance_name}_tb import ${module_instance_name}_reg_pkg::*; #(
input rst_ni,
input tlul_pkg::tl_h2d_t [NumInstances-1:0] tl_i,
output tlul_pkg::tl_d2h_t [NumInstances-1:0] tl_o,
input [NumInstances-1:0][NumSrc-1:0] intr_src_i,
input [NumInstances-1:0][NumSrc-2:0] intr_src_nonzero_i,
input prim_alert_pkg::alert_rx_t [NumInstances-1:0][NumAlerts-1:0] alert_rx_i,
output prim_alert_pkg::alert_tx_t [NumInstances-1:0][NumAlerts-1:0] alert_tx_o,
output [NumInstances-1:0][NumTarget-1:0] irq_o,
Expand All @@ -29,7 +29,8 @@ module ${module_instance_name}_tb import ${module_instance_name}_reg_pkg::*; #(
.rst_ni ,
.tl_i (tl_i[0]),
.tl_o (tl_o[0]),
.intr_src_i (intr_src_i[0]),
// Interrupt 0 must be tied to 0.
.intr_src_i ({intr_src_nonzero_i[0], 1'b0}),
.alert_rx_i (alert_rx_i[0]),
.alert_tx_o (alert_tx_o[0]),
.irq_o (irq_o[0]),
Expand Down
8 changes: 5 additions & 3 deletions hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl
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Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,9 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #(
output top_racl_pkg::racl_error_log_t racl_error_o,
% endif

// Interrupt Sources
// Interrupt Sources. Note that the lowest bit must be tied to 0 because it
// is reserved for "no interrupt". Because the lowest bit is always 0,
// only NumSrc-1 interrupts are usable.
input [NumSrc-1:0] intr_src_i,

// Alerts
Expand Down Expand Up @@ -283,8 +285,8 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #(
`ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o[k])
end

// Assume
`ASSUME(Irq0Tied_A, intr_src_i[0] == 1'b0)
// Bit 0 must be tied to zero because it is reserved for "no interrupt".
`ASSERT(Irq0Tied_A, intr_src_i[0] == 1'b0)

// This assertion should be provable in FPV because we don't have a block-level DV environment. It
// is trying to say that any integrity error detected inside the register block (u_reg) will cause
Expand Down
3 changes: 3 additions & 0 deletions hw/top_darjeeling/ip_autogen/rv_plic/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,9 @@ The RV_PLIC module is designed to manage various interrupt sources from the
peripherals. It receives interrupt events as either edge or level of the
incoming interrupt signals (``intr_src_i``) and can notify multiple targets.

Note that the lowest bit of ``intr_src_i`` is must be tied to 0 because it corresponds interrupt ID 0 which is reserved to mean "no interrupt". This is
verified with an assertion inside `rv_plic`.

## Compatibility

The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification.
2 changes: 1 addition & 1 deletion hw/top_darjeeling/ip_autogen/rv_plic/data/rv_plic.hjson
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@

param_list: [
{ name: "NumSrc",
desc: "Number of interrupt sources",
desc: "Number of interrupt sources (including the 'no interrupt' ID 0)",
type: "int",
default: "132",
local: "true"
Expand Down
5 changes: 3 additions & 2 deletions hw/top_darjeeling/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ module rv_plic_tb import rv_plic_reg_pkg::*; #(
input rst_ni,
input tlul_pkg::tl_h2d_t [NumInstances-1:0] tl_i,
output tlul_pkg::tl_d2h_t [NumInstances-1:0] tl_o,
input [NumInstances-1:0][NumSrc-1:0] intr_src_i,
input [NumInstances-1:0][NumSrc-2:0] intr_src_nonzero_i,
input prim_alert_pkg::alert_rx_t [NumInstances-1:0][NumAlerts-1:0] alert_rx_i,
output prim_alert_pkg::alert_tx_t [NumInstances-1:0][NumAlerts-1:0] alert_tx_o,
output [NumInstances-1:0][NumTarget-1:0] irq_o,
Expand All @@ -29,7 +29,8 @@ module rv_plic_tb import rv_plic_reg_pkg::*; #(
.rst_ni ,
.tl_i (tl_i[0]),
.tl_o (tl_o[0]),
.intr_src_i (intr_src_i[0]),
// Interrupt 0 must be tied to 0.
.intr_src_i ({intr_src_nonzero_i[0], 1'b0}),
.alert_rx_i (alert_rx_i[0]),
.alert_tx_o (alert_tx_o[0]),
.irq_o (irq_o[0]),
Expand Down
8 changes: 5 additions & 3 deletions hw/top_darjeeling/ip_autogen/rv_plic/rtl/rv_plic.sv
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Expand Up @@ -36,7 +36,9 @@ module rv_plic import rv_plic_reg_pkg::*; #(
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,

// Interrupt Sources
// Interrupt Sources. Note that the lowest bit must be tied to 0 because it
// is reserved for "no interrupt". Because the lowest bit is always 0,
// only NumSrc-1 interrupts are usable.
input [NumSrc-1:0] intr_src_i,

// Alerts
Expand Down Expand Up @@ -376,8 +378,8 @@ module rv_plic import rv_plic_reg_pkg::*; #(
`ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o[k])
end

// Assume
`ASSUME(Irq0Tied_A, intr_src_i[0] == 1'b0)
// Bit 0 must be tied to zero because it is reserved for "no interrupt".
`ASSERT(Irq0Tied_A, intr_src_i[0] == 1'b0)

// This assertion should be provable in FPV because we don't have a block-level DV environment. It
// is trying to say that any integrity error detected inside the register block (u_reg) will cause
Expand Down
3 changes: 3 additions & 0 deletions hw/top_earlgrey/ip_autogen/rv_plic/README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,9 @@ The RV_PLIC module is designed to manage various interrupt sources from the
peripherals. It receives interrupt events as either edge or level of the
incoming interrupt signals (``intr_src_i``) and can notify multiple targets.

Note that the lowest bit of ``intr_src_i`` is must be tied to 0 because it corresponds interrupt ID 0 which is reserved to mean "no interrupt". This is
verified with an assertion inside `rv_plic`.

## Compatibility

The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification.
2 changes: 1 addition & 1 deletion hw/top_earlgrey/ip_autogen/rv_plic/data/rv_plic.hjson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@

param_list: [
{ name: "NumSrc",
desc: "Number of interrupt sources",
desc: "Number of interrupt sources (including the 'no interrupt' ID 0)",
type: "int",
default: "186",
local: "true"
Expand Down
5 changes: 3 additions & 2 deletions hw/top_earlgrey/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ module rv_plic_tb import rv_plic_reg_pkg::*; #(
input rst_ni,
input tlul_pkg::tl_h2d_t [NumInstances-1:0] tl_i,
output tlul_pkg::tl_d2h_t [NumInstances-1:0] tl_o,
input [NumInstances-1:0][NumSrc-1:0] intr_src_i,
input [NumInstances-1:0][NumSrc-2:0] intr_src_nonzero_i,
input prim_alert_pkg::alert_rx_t [NumInstances-1:0][NumAlerts-1:0] alert_rx_i,
output prim_alert_pkg::alert_tx_t [NumInstances-1:0][NumAlerts-1:0] alert_tx_o,
output [NumInstances-1:0][NumTarget-1:0] irq_o,
Expand All @@ -29,7 +29,8 @@ module rv_plic_tb import rv_plic_reg_pkg::*; #(
.rst_ni ,
.tl_i (tl_i[0]),
.tl_o (tl_o[0]),
.intr_src_i (intr_src_i[0]),
// Interrupt 0 must be tied to 0.
.intr_src_i ({intr_src_nonzero_i[0], 1'b0}),
.alert_rx_i (alert_rx_i[0]),
.alert_tx_o (alert_tx_o[0]),
.irq_o (irq_o[0]),
Expand Down
8 changes: 5 additions & 3 deletions hw/top_earlgrey/ip_autogen/rv_plic/rtl/rv_plic.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,9 @@ module rv_plic import rv_plic_reg_pkg::*; #(
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,

// Interrupt Sources
// Interrupt Sources. Note that the lowest bit must be tied to 0 because it
// is reserved for "no interrupt". Because the lowest bit is always 0,
// only NumSrc-1 interrupts are usable.
input [NumSrc-1:0] intr_src_i,

// Alerts
Expand Down Expand Up @@ -430,8 +432,8 @@ module rv_plic import rv_plic_reg_pkg::*; #(
`ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o[k])
end

// Assume
`ASSUME(Irq0Tied_A, intr_src_i[0] == 1'b0)
// Bit 0 must be tied to zero because it is reserved for "no interrupt".
`ASSERT(Irq0Tied_A, intr_src_i[0] == 1'b0)

// This assertion should be provable in FPV because we don't have a block-level DV environment. It
// is trying to say that any integrity error detected inside the register block (u_reg) will cause
Expand Down
3 changes: 3 additions & 0 deletions hw/top_englishbreakfast/ip_autogen/rv_plic/README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,9 @@ The RV_PLIC module is designed to manage various interrupt sources from the
peripherals. It receives interrupt events as either edge or level of the
incoming interrupt signals (``intr_src_i``) and can notify multiple targets.

Note that the lowest bit of ``intr_src_i`` is must be tied to 0 because it corresponds interrupt ID 0 which is reserved to mean "no interrupt". This is
verified with an assertion inside `rv_plic`.

## Compatibility

The RV_PLIC is compatible with any RISC-V core implementing the RISC-V privilege specification.
2 changes: 1 addition & 1 deletion hw/top_englishbreakfast/ip_autogen/rv_plic/data/rv_plic.hjson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@

param_list: [
{ name: "NumSrc",
desc: "Number of interrupt sources",
desc: "Number of interrupt sources (including the 'no interrupt' ID 0)",
type: "int",
default: "88",
local: "true"
Expand Down
5 changes: 3 additions & 2 deletions hw/top_englishbreakfast/ip_autogen/rv_plic/fpv/tb/rv_plic_tb.sv
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ module rv_plic_tb import rv_plic_reg_pkg::*; #(
input rst_ni,
input tlul_pkg::tl_h2d_t [NumInstances-1:0] tl_i,
output tlul_pkg::tl_d2h_t [NumInstances-1:0] tl_o,
input [NumInstances-1:0][NumSrc-1:0] intr_src_i,
input [NumInstances-1:0][NumSrc-2:0] intr_src_nonzero_i,
input prim_alert_pkg::alert_rx_t [NumInstances-1:0][NumAlerts-1:0] alert_rx_i,
output prim_alert_pkg::alert_tx_t [NumInstances-1:0][NumAlerts-1:0] alert_tx_o,
output [NumInstances-1:0][NumTarget-1:0] irq_o,
Expand All @@ -29,7 +29,8 @@ module rv_plic_tb import rv_plic_reg_pkg::*; #(
.rst_ni ,
.tl_i (tl_i[0]),
.tl_o (tl_o[0]),
.intr_src_i (intr_src_i[0]),
// Interrupt 0 must be tied to 0.
.intr_src_i ({intr_src_nonzero_i[0], 1'b0}),
.alert_rx_i (alert_rx_i[0]),
.alert_tx_o (alert_tx_o[0]),
.irq_o (irq_o[0]),
Expand Down
8 changes: 5 additions & 3 deletions hw/top_englishbreakfast/ip_autogen/rv_plic/rtl/rv_plic.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,9 @@ module rv_plic import rv_plic_reg_pkg::*; #(
input tlul_pkg::tl_h2d_t tl_i,
output tlul_pkg::tl_d2h_t tl_o,

// Interrupt Sources
// Interrupt Sources. Note that the lowest bit must be tied to 0 because it
// is reserved for "no interrupt". Because the lowest bit is always 0,
// only NumSrc-1 interrupts are usable.
input [NumSrc-1:0] intr_src_i,

// Alerts
Expand Down Expand Up @@ -332,8 +334,8 @@ module rv_plic import rv_plic_reg_pkg::*; #(
`ASSERT_KNOWN(IrqIdKnownO_A, irq_id_o[k])
end

// Assume
`ASSUME(Irq0Tied_A, intr_src_i[0] == 1'b0)
// Bit 0 must be tied to zero because it is reserved for "no interrupt".
`ASSERT(Irq0Tied_A, intr_src_i[0] == 1'b0)

// This assertion should be provable in FPV because we don't have a block-level DV environment. It
// is trying to say that any integrity error detected inside the register block (u_reg) will cause
Expand Down
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