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12 Open 242 Closed
12 Open 242 Closed
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Issues list

Cannot simulate with QuestaSim
#891 opened Jul 17, 2019 by BasF0
3
Using Multiple Banks in DDR to Enable Multiple Read/Write at Same Cycle nice to have question
#890 opened Jul 11, 2019 by yuanm2
1
SW Action not running when using snap_action_start specific API nice to have
#888 opened Jul 2, 2019 by sinitame
bus error on deployment of an action that passes pslse
#882 opened May 10, 2019 by diamantopoulos
@bmesnet
4
Support simulating SNAP actions using Vivado WebPACK nice to have
#821 opened Sep 26, 2018 by rs22
1
make clean conflicts with per action "user IP" enhancement verify
#798 opened Aug 17, 2018 by david-mle
6
SR10441909: xsim: writememh() works in combination with sformat() and readmemh() does not bug in progress Xilinx_SRs
#766 opened Jul 6, 2018 by fhaverkamp
@joergkayser
9
AXI4 arlock/awlock has width of 2 bits instead of 1 bit bug nice to have
#758 opened Jun 27, 2018 by johanpel
@ThomasFuchs
1
Integrate AXI protocol checkers enhancement
#756 opened Jun 26, 2018 by johanpel
@boekholt
1
NVMe: high level model - review findings enhancement
#748 opened Jun 12, 2018 by boekholt
8 tasks
@fhaverkamp @boekholt
NVMe: High-level model for SNAP NVMe Support multiple operations in parallel enhancement
#739 opened May 16, 2018 by fhaverkamp
@fhaverkamp
Enable the 2nd DRAM controller for ADKU3 and S121B cards enhancement
#619 opened Feb 8, 2018 by jsvogt
@ThomasFuchs @luyong6
4
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