Major Changes
No major changes - Still Vivado2018.1 is supported for both CAPI1.0 and CAPI2.0
Changes relative to v1.5.0
- Documentation updates
- add waveforms for debugging (#833)
- New example: hdl example added (#838)
- New example: hls_decimal_mult (#826)
- Add mechanism to specify HLS compiler flags in action hw Makefile
- Adapt SNAP build process to HLS Xilinx IP call
- Update 8K5 PSL rev006 to rev007
- Adding 2 VU9P cards (FX609/S241)
- Add memcpy_throughputs tests (#784)
- Use a 34 bits address width for nvme_ddr
- Implement full CAPI2.0 DMA performance (#771)
- NVMe: attempt to circumvent Xilinx SystemVerilog deficiency + fixing synthesis problem
- Simplify use of snap_env.sh variables (#764)
- Get rid of Critical warnings in create_nvme_host.tcl
- Adapting SNAP build process to capi2-bsp
- Enable S121B card (SPIx4 and BPIx16)