v0.5.2

Fix the version number.

v0.5.1

• Wording update
  • Typo fixes
  • General update to improve clearance
  • Replace "submachine" to "supervisor domain"
  • Replace "machine mode" to "M-mode"
  • Remove the hart index i
• Add notes to clarify the scenario when the debug control changes dynamically in section 3.1
• Add notes to elaborate on dmode in in section 3.3.1
• Add a list to summarize the changes made to debug and trace spec in chapter 1
• Add Terminology in section 1.1
• Abstract Command without halting cause cmderr set to 6 in section 3.1
• Include memory access without halting behavior in section 3.1
• Make stepie accessible in debug mode and only affect the interrupt delegated to debug-allowed privilege in section 3.1.5
• Replace trace input signal details with a generalized normative description in section 3.2.1
• Add description for conditions where triggers are not configurable in section 3.3
• Define that the external trigger inputs are constrained by source from where it is generated in section 3.3.2
• Eliminate the exceptional CSR access rule and introduce S-mode debug CSRs in section 3.4.1
• Extend the discovery method in section 4.1
• Halt-on-reset will be pending till first debuggable instruction in section 4.2
• Keepalive will not raise error in section 4.4
• Quick Access raises error (cmderr=6) when M-mode debug is disallowed in section 4.5.3
• Change error status to be sticky and add acksecfault bit to clear error status in section 4.7
• Add a system-level control knob nsecdbg that enables full debugging capability in section 4.8
• Change spec name from "RISC-V External Debug Security Extension" to "RISC-V External Debug Security Specification"
• Update copyright
• Update reference

What's Changed

• Change naming of the ISA spec by @joxie in #30
• Positions of any/all changed for secured/secfaults in dmstatus by @gokhankaplayan in #28
• • Specify the UNSPECIFIED behavior for privilege changing instructions by @AoteJin in #32
• • Make secfault optional for illegal value of prv/v in dcsr by @AoteJin in #33
• • Update the wording and add change overview in intro by @AoteJin in #38
• • Add Terminology subsection by @AoteJin in #39
• Wording update by @AoteJin in #42
• Wording update by @AoteJin in #43
• • Wording update for non-ISA extension by @AoteJin in #44
• • Make the prv and v in dcsr WARL and eliminate secfault error by @AoteJin in #45
• Update based on Rev0.5 feedbacks by @AoteJin in #47
• • Remove the wrong description by @AoteJin in #52
• Add trigger delegation spec (temporarily) by @bcstrongx in #54
• • Update the trace description by removing the interface signal details by @AoteJin in #53
• Revisions from feedback on Smtdeleg/Sstcfg by @bcstrongx in #55
• Add stselect to regs whose access is controlled by xstateen0.TR by @bcstrongx in #57
• • Add system level control knob which allows full debugging capability by @AoteJin in #56
• modify warn blocks by @bcstrongx in #59
• Avoid 2-level redirection description in Smtdeleg/Sstcfg spec by @bcstrongx in #61
• • Add S-mode debug CSR for debug by @AoteJin in #60
• Update the intro and appendix by @AoteJin in #62

New Contributors

• @gokhankaplayan made their first contribution in #28
• @bcstrongx made their first contribution in #54

Full Changelog: v0.5.0...v0.5.1

v0.5.0

Initial draft release. Spec ready to start POC project.

What's Changed

• Start a PR to commit initial draft by @AoteJin in #2
• Initial commit by @joxie in #3
• Add the threat model chapter and diagram by @AoteJin in #4
• • Fix typo in diagram by @AoteJin in #6
• Rev0.5 by @joxie in #7
• Change the trace signal that will be driven for security control to address issue #11 by @AoteJin in #18
• Trace ctl sig by @joxie in #19
• Update according to issues by @AoteJin in #25
• Add notes for homogeneous computing system by @AoteJin in #26

New Contributors

• @joxie made their first contribution in #3

Full Changelog: https://github.com/riscv-non-isa/riscv-external-debug-security/commits/v0.5.0