v0.5.0

Initial draft release. Spec ready to start POC project.

What's Changed

• Start a PR to commit initial draft by @AoteJin in #2
• Initial commit by @joxie in #3
• Add the threat model chapter and diagram by @AoteJin in #4
• • Fix typo in diagram by @AoteJin in #6
• Rev0.5 by @joxie in #7
• Change the trace signal that will be driven for security control to address issue #11 by @AoteJin in #18
• Trace ctl sig by @joxie in #19
• Update according to issues by @AoteJin in #25
• Add notes for homogeneous computing system by @AoteJin in #26

New Contributors

• @joxie made their first contribution in #3

Full Changelog: https://github.com/riscv-non-isa/riscv-external-debug-security/commits/v0.5.0