"Q" extension

[LiuTaowen-Tony]

Hi, I create this merge request just to tell that somebody is working on the "Q" extension. There is no test for the "Q" extension in the open-source riscv-test project. I am still working on the riscv-test project. The progress is slow because the current riscv toolchain doesn't support 128-bit floating point arithmetic well.

I know that there are still incompatibilities and git usage is not good. I will fix them after I finish the riscv test for the "Q" extension.

[billmcspadden-riscv]

Hi Liu. Your announcement that you are working on the Q extension is quite timely. I was just talking with Allen Baum and Bilal Sakhawat about this last evening. I am Bill McSpadden, and I work for RISC-V International as one of the keepers of the RISC-V Sail model (Martin Berger being the other designated keeper). We have a regular bi-weekly meeting to discuss the model. Subscribe to the tech-golden-model group to receive emails regarding our meetings. We'd very much like to have you join our meetings. Our next meeting will be Tuesday, Nov. 1st at 6am Central Time, US. In which time zone do you work? Do you think that you can attend? Bill Mc.

…

On Thu, Oct 20, 2022 at 9:16 AM Liu ***@***.***> wrote: Hi, I create this merge request just to tell that somebody is working on the "Q" extension. There is no test for the "Q" extension in the open-source riscv-test project. I am still working on the riscv-test project. The progress is slow because the current riscv toolchain doesn't support 128-bit floating point arithmetic well. I know that there are still incompatibilities and git usage is not good. I will fix them after I finish the riscv test for the "Q" extension. ------------------------------ You can view, comment on, or merge this pull request online at: #187 Commit Summary - 221409e <221409e> made it compile on my computer - aba4d17 <aba4d17> adjusted nan_box so that they can wrap and unwrap 128bits - 37f1b30 <37f1b30> added flen = 128 into the model - 09517f2 <09517f2> adjusted load and store in riscv_insts_{dext,fext,zfh}.sail to pass the tests - e12522c <e12522c> implemented load_fp_q - b68f612 <b68f612> added a madd instruction for q extension - 6fd30bf <6fd30bf> added QUAD to word_width - a11795a <a11795a> implemented fstore for quad precision numbers - ac69a15 <ac69a15> have fclass.q fmin.q fmax.q remaining - a572821 <a572821> added fmin fmax fclass File Changes (29 files <https://github.com/riscv/sail-riscv/pull/187/files>) - *A* .vscode/asdf.code-snippets <https://github.com/riscv/sail-riscv/pull/187/files#diff-5b045467f5f52bc92e59e1ae7f175f6456f28bd86745447c133685d1e0b4183c> (30) - *A* .vscode/settings.json <https://github.com/riscv/sail-riscv/pull/187/files#diff-a5de3e5871ffcc383a2294845bd3df25d3eeff6c29ad46e3a396577c413bf357> (10) - *M* Makefile <https://github.com/riscv/sail-riscv/pull/187/files#diff-76ed074a9305c04054cdebb9e9aad2d818052b07091de1f20cad0bbac34ffb52> (11) - *M* c_emulator/SoftFloat-3e/source/include/softfloat.h <https://github.com/riscv/sail-riscv/pull/187/files#diff-9201e50aebf3604313b8f35f752f7fd6083af29169221a9deed62057a406b9d4> (42) - *M* c_emulator/riscv_sail.h <https://github.com/riscv/sail-riscv/pull/187/files#diff-578d12420767e6b63aecdfaefcd0b6c866c9f3e83ed4923aab74ac3bc287e564> (7) - *A* c_emulator/riscv_sim_RV32.dSYM/Contents/Info.plist <https://github.com/riscv/sail-riscv/pull/187/files#diff-051a9946ee8a0739862e1d9c9dc0fa8e400b31043c1dbfe425ca9390482ea9b1> (20) - *A* c_emulator/riscv_sim_RV32.dSYM/Contents/Resources/DWARF/riscv_sim_RV32 <https://github.com/riscv/sail-riscv/pull/187/files#diff-23e416c7eab64caa1a6d3af50e06a104e01c0fd11949d1535f3d170faab99ca1> (0) - *A* c_emulator/riscv_sim_RV64.dSYM/Contents/Info.plist <https://github.com/riscv/sail-riscv/pull/187/files#diff-8ed8dacd26906c6967e9f9231cc6db1f76115b0b3f14db8db5917f5adc03b396> (20) - *A* c_emulator/riscv_sim_RV64.dSYM/Contents/Resources/DWARF/riscv_sim_RV64 <https://github.com/riscv/sail-riscv/pull/187/files#diff-350f9e60d2744eaaed21af93a56f71d80704a81adfb5e6197d23a4a2f55baaf1> (0) - *M* c_emulator/riscv_softfloat.c <https://github.com/riscv/sail-riscv/pull/187/files#diff-6d8de867981a4765e49b79219b9f0aa57cb09a0fb7fd88eb16b94e518fc148c1> (358) - *M* c_emulator/riscv_softfloat.h <https://github.com/riscv/sail-riscv/pull/187/files#diff-9f5bf5e6685c80adbd482e33a5aa3b44fa219ccbe9d5238b3fde08b08a84d9f7> (27) - *M* model/riscv_fdext_regs.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-3787c9adfa214eebf05797975eb1f94785e374ddf881434c0ade1460013279c1> (90) - *A* model/riscv_flen_Q.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-f628e09121152d802f61f913b2361421daf5e2c26906ee70f26ea3bb2bf89c2a> (73) - *M* model/riscv_freg_type.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-ccd333d2e71baaae461939e318dcbfe0e8bceef0d2765d39c5e1fa981e57f0ab> (12) - *M* model/riscv_insts_base.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-79f206b24355b43cbad5f78d3732a93a32352f80f41c756b24ff08f7c00239dd> (3) - *M* model/riscv_insts_dext.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-fca55fae4dabc345c8b78ac7f957dc7fea86bb4c496a6273491d25be7bf9ad18> (2) - *M* model/riscv_insts_fext.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-3191f3091845a35899eebc33d3a08748e5bb47b37a477cd2ca42e3f9084aee1a> (47) - *A* model/riscv_insts_qext.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-51a93478585e4b810ac7c7125af4ce6962bdf0f11176ee5ae4b890cd7bbf2644> (995) - *A* model/riscv_insts_qext_.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-d4e3bfeab51655de4a6e7578981063ca98eefe61739766447dca27000ed095b4> (1083) - *M* model/riscv_insts_zfh.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-89396b657ba6298079c7c9c2fec702dae6f018c8464bbe4b0f58720535a22279> (4) - *M* model/riscv_softfloat_interface.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-886be3c739e989aac99f1d910e399bb797424940790bfad6daa6e60736677f48> (190) - *M* model/riscv_sys_regs.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-e1a3fe7050c3af4c308a5e39bfb7f0f31094022b9892cee9a611bcb57ccb6726> (3) - *M* model/riscv_types.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-395d83a6b080a45d2a434a560f62b03df797180267f434e5fe3f4d66d971544f> (33) - *M* ocaml_emulator/platform_impl.ml <https://github.com/riscv/sail-riscv/pull/187/files#diff-d3f12b492b96e70b934521a800fe3d6a891385073841b086c7818fe9e73c4a10> (2) - *M* ocaml_emulator/softfloat.ml <https://github.com/riscv/sail-riscv/pull/187/files#diff-359c83d8558856b3b38a95916667fab78d35a1e406aa875d11de5d6e70c4c400> (65) - *A* run_test_out.txt <https://github.com/riscv/sail-riscv/pull/187/files#diff-fc951ae60325c4a4f5c5fc102be7314289d3b6491a1cafe540a6ef3da2f1b39f> (0) - *A* test/fp_tests_out.txt <https://github.com/riscv/sail-riscv/pull/187/files#diff-22cb9125eaf4b57f4d5974d784a9f1eba07f700b15308aadd0472a3fe4f83b83> (403) - *A* test/run_test_out.txt <https://github.com/riscv/sail-riscv/pull/187/files#diff-ed7c4b78f11f950f6e52e9ef3795c655cd05d80c867ab3ae8b54e5a44de04117> (792) - *A* z3_problems <https://github.com/riscv/sail-riscv/pull/187/files#diff-29c4731f7aa90acd1e34cae91c39a0fc49b91cca3889ee85b86a2de57f060884> (0) Patch Links: - https://github.com/riscv/sail-riscv/pull/187.patch - https://github.com/riscv/sail-riscv/pull/187.diff — Reply to this email directly, view it on GitHub <#187>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AXROLOGJTSXXKQ5KBMWOXZ3WEFH4PANCNFSM6AAAAAARKGOW5E> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

-- Bill McSpadden Formal Verification Engineer RISC-V International mobile: 503-807-9309

[LiuTaowen-Tony]

Hi Bill, Thank you very much for inviting me to the meeting. II am very glad to attend the meeting and look forward to discussing more details during the meeting. I am in UK currently. So I think the meeting time for me would be 11.00 on Nov 1st. Thank you for helping me on this project! Best wishes, Tony 2022年10月20日 16:41，Bill McSpadden ***@***.******@***.***>> 写道： Hi Liu. Your announcement that you are working on the Q extension is quite timely. I was just talking with Allen Baum and Bilal Sakhawat about this last evening. I am Bill McSpadden, and I work for RISC-V International as one of the keepers of the RISC-V Sail model (Martin Berger being the other designated keeper). We have a regular bi-weekly meeting to discuss the model. Subscribe to the tech-golden-model group to receive emails regarding our meetings. We'd very much like to have you join our meetings. Our next meeting will be Tuesday, Nov. 1st at 6am Central Time, US. In which time zone do you work? Do you think that you can attend? Bill Mc.

…

On Thu, Oct 20, 2022 at 9:16 AM Liu ***@***.***> wrote: Hi, I create this merge request just to tell that somebody is working on the "Q" extension. There is no test for the "Q" extension in the open-source riscv-test project. I am still working on the riscv-test project. The progress is slow because the current riscv toolchain doesn't support 128-bit floating point arithmetic well. I know that there are still incompatibilities and git usage is not good. I will fix them after I finish the riscv test for the "Q" extension. ------------------------------ You can view, comment on, or merge this pull request online at: #187 Commit Summary - 221409e <221409e> made it compile on my computer - aba4d17 <aba4d17> adjusted nan_box so that they can wrap and unwrap 128bits - 37f1b30 <37f1b30> added flen = 128 into the model - 09517f2 <09517f2> adjusted load and store in riscv_insts_{dext,fext,zfh}.sail to pass the tests - e12522c <e12522c> implemented load_fp_q - b68f612 <b68f612> added a madd instruction for q extension - 6fd30bf <6fd30bf> added QUAD to word_width - a11795a <a11795a> implemented fstore for quad precision numbers - ac69a15 <ac69a15> have fclass.q fmin.q fmax.q remaining - a572821 <a572821> added fmin fmax fclass File Changes (29 files <https://github.com/riscv/sail-riscv/pull/187/files>) - *A* .vscode/asdf.code-snippets <https://github.com/riscv/sail-riscv/pull/187/files#diff-5b045467f5f52bc92e59e1ae7f175f6456f28bd86745447c133685d1e0b4183c> (30) - *A* .vscode/settings.json <https://github.com/riscv/sail-riscv/pull/187/files#diff-a5de3e5871ffcc383a2294845bd3df25d3eeff6c29ad46e3a396577c413bf357> (10) - *M* Makefile <https://github.com/riscv/sail-riscv/pull/187/files#diff-76ed074a9305c04054cdebb9e9aad2d818052b07091de1f20cad0bbac34ffb52> (11) - *M* c_emulator/SoftFloat-3e/source/include/softfloat.h <https://github.com/riscv/sail-riscv/pull/187/files#diff-9201e50aebf3604313b8f35f752f7fd6083af29169221a9deed62057a406b9d4> (42) - *M* c_emulator/riscv_sail.h <https://github.com/riscv/sail-riscv/pull/187/files#diff-578d12420767e6b63aecdfaefcd0b6c866c9f3e83ed4923aab74ac3bc287e564> (7) - *A* c_emulator/riscv_sim_RV32.dSYM/Contents/Info.plist <https://github.com/riscv/sail-riscv/pull/187/files#diff-051a9946ee8a0739862e1d9c9dc0fa8e400b31043c1dbfe425ca9390482ea9b1> (20) - *A* c_emulator/riscv_sim_RV32.dSYM/Contents/Resources/DWARF/riscv_sim_RV32 <https://github.com/riscv/sail-riscv/pull/187/files#diff-23e416c7eab64caa1a6d3af50e06a104e01c0fd11949d1535f3d170faab99ca1> (0) - *A* c_emulator/riscv_sim_RV64.dSYM/Contents/Info.plist <https://github.com/riscv/sail-riscv/pull/187/files#diff-8ed8dacd26906c6967e9f9231cc6db1f76115b0b3f14db8db5917f5adc03b396> (20) - *A* c_emulator/riscv_sim_RV64.dSYM/Contents/Resources/DWARF/riscv_sim_RV64 <https://github.com/riscv/sail-riscv/pull/187/files#diff-350f9e60d2744eaaed21af93a56f71d80704a81adfb5e6197d23a4a2f55baaf1> (0) - *M* c_emulator/riscv_softfloat.c <https://github.com/riscv/sail-riscv/pull/187/files#diff-6d8de867981a4765e49b79219b9f0aa57cb09a0fb7fd88eb16b94e518fc148c1> (358) - *M* c_emulator/riscv_softfloat.h <https://github.com/riscv/sail-riscv/pull/187/files#diff-9f5bf5e6685c80adbd482e33a5aa3b44fa219ccbe9d5238b3fde08b08a84d9f7> (27) - *M* model/riscv_fdext_regs.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-3787c9adfa214eebf05797975eb1f94785e374ddf881434c0ade1460013279c1> (90) - *A* model/riscv_flen_Q.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-f628e09121152d802f61f913b2361421daf5e2c26906ee70f26ea3bb2bf89c2a> (73) - *M* model/riscv_freg_type.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-ccd333d2e71baaae461939e318dcbfe0e8bceef0d2765d39c5e1fa981e57f0ab> (12) - *M* model/riscv_insts_base.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-79f206b24355b43cbad5f78d3732a93a32352f80f41c756b24ff08f7c00239dd> (3) - *M* model/riscv_insts_dext.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-fca55fae4dabc345c8b78ac7f957dc7fea86bb4c496a6273491d25be7bf9ad18> (2) - *M* model/riscv_insts_fext.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-3191f3091845a35899eebc33d3a08748e5bb47b37a477cd2ca42e3f9084aee1a> (47) - *A* model/riscv_insts_qext.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-51a93478585e4b810ac7c7125af4ce6962bdf0f11176ee5ae4b890cd7bbf2644> (995) - *A* model/riscv_insts_qext_.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-d4e3bfeab51655de4a6e7578981063ca98eefe61739766447dca27000ed095b4> (1083) - *M* model/riscv_insts_zfh.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-89396b657ba6298079c7c9c2fec702dae6f018c8464bbe4b0f58720535a22279> (4) - *M* model/riscv_softfloat_interface.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-886be3c739e989aac99f1d910e399bb797424940790bfad6daa6e60736677f48> (190) - *M* model/riscv_sys_regs.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-e1a3fe7050c3af4c308a5e39bfb7f0f31094022b9892cee9a611bcb57ccb6726> (3) - *M* model/riscv_types.sail <https://github.com/riscv/sail-riscv/pull/187/files#diff-395d83a6b080a45d2a434a560f62b03df797180267f434e5fe3f4d66d971544f> (33) - *M* ocaml_emulator/platform_impl.ml <https://github.com/riscv/sail-riscv/pull/187/files#diff-d3f12b492b96e70b934521a800fe3d6a891385073841b086c7818fe9e73c4a10> (2) - *M* ocaml_emulator/softfloat.ml <https://github.com/riscv/sail-riscv/pull/187/files#diff-359c83d8558856b3b38a95916667fab78d35a1e406aa875d11de5d6e70c4c400> (65) - *A* run_test_out.txt <https://github.com/riscv/sail-riscv/pull/187/files#diff-fc951ae60325c4a4f5c5fc102be7314289d3b6491a1cafe540a6ef3da2f1b39f> (0) - *A* test/fp_tests_out.txt <https://github.com/riscv/sail-riscv/pull/187/files#diff-22cb9125eaf4b57f4d5974d784a9f1eba07f700b15308aadd0472a3fe4f83b83> (403) - *A* test/run_test_out.txt <https://github.com/riscv/sail-riscv/pull/187/files#diff-ed7c4b78f11f950f6e52e9ef3795c655cd05d80c867ab3ae8b54e5a44de04117> (792) - *A* z3_problems <https://github.com/riscv/sail-riscv/pull/187/files#diff-29c4731f7aa90acd1e34cae91c39a0fc49b91cca3889ee85b86a2de57f060884> (0) Patch Links: - https://github.com/riscv/sail-riscv/pull/187.patch - https://github.com/riscv/sail-riscv/pull/187.diff — Reply to this email directly, view it on GitHub <#187>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AXROLOGJTSXXKQ5KBMWOXZ3WEFH4PANCNFSM6AAAAAARKGOW5E> . You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>

-- Bill McSpadden Formal Verification Engineer RISC-V International mobile: 503-807-9309 — Reply to this email directly, view it on GitHub<#187 (comment)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AJQOH3VEN4CGQGAXB7XAWLLWEFR2XANCNFSM6AAAAAARKGOW5E>. You are receiving this because you authored the thread.Message ID: ***@***.***>

[LiuTaowen-Tony]

Hi Bill,

Thanks again for the invitation to the meeting. However, I am not quite sure what will be specifically discussed in the meeting. Do I need to do some preparation for reporting what I have done? Since there was a long time I haven't touch the code. I need to review what I have done before the meeting.

Thank you,
Tony

[jordancarlin]

Closing as this has been superseded by #445