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Q extension #445

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2 changes: 1 addition & 1 deletion CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -125,7 +125,7 @@ execute_process(
)
message(STATUS "Sail library directory: ${sail_dir}")

set(DEFAULT_ARCHITECTURES "rv32d;rv64d" CACHE STRING "Architectures to build by default (rv32f|rv64f|rv32d|rv64d)(_rvfi)? " )
set(DEFAULT_ARCHITECTURES "rv32d;rv64d" CACHE STRING "Architectures to build by default (rv32f|rv64f|rv32d|rv64d|rv32q|rv64q)(_rvfi)? " )

option(COVERAGE "Compile with Sail coverage collection enabled.")

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13 changes: 12 additions & 1 deletion Makefile.old
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@

# Select architecture: RV32 or RV64.
ARCH ?= RV64
FLEN ?= 64

ifeq ($(ARCH),32)
override ARCH := RV32
Expand All @@ -21,8 +22,17 @@ else
$(error '$(ARCH)' is not a valid architecture, must be one of: RV32, RV64)
endif

ifeq ($(FLEN),32)
SAIL_FLEN := riscv_flen_F.sail
else ifeq ($(FLEN),64)
SAIL_FLEN := riscv_flen_D.sail
else ifeq ($(FLEN),128)
SAIL_FLEN := riscv_flen_Q.sail
else
$(error '$(FLEN)' is not a valid value for FLEN, must be one of: 32, 64, 128)
endif

SAIL_XLEN += riscv_xlen.sail
SAIL_FLEN := riscv_flen_D.sail
SAIL_FLEN += riscv_flen.sail
SAIL_VLEN := riscv_vlen.sail

Expand All @@ -31,6 +41,7 @@ SAIL_CHECK_SRCS = riscv_addr_checks_common.sail riscv_addr_checks.sail riscv_mis
SAIL_DEFAULT_INST = riscv_insts_base.sail riscv_insts_zifencei.sail riscv_insts_aext.sail riscv_insts_zca.sail riscv_insts_mext.sail riscv_insts_zicsr.sail riscv_insts_hints.sail
SAIL_DEFAULT_INST += riscv_insts_fext.sail riscv_insts_zcf.sail
SAIL_DEFAULT_INST += riscv_insts_dext.sail riscv_insts_zcd.sail
SAIL_DEFAULT_INST += riscv_insts_qext.sail

SAIL_DEFAULT_INST += riscv_insts_svinval.sail

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6 changes: 4 additions & 2 deletions c_emulator/CMakeLists.txt
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Expand Up @@ -15,13 +15,15 @@ set(EMULATOR_COMMON_SRCS
)

foreach (xlen IN ITEMS 32 64)
foreach (flen IN ITEMS 32 64)
foreach (flen IN ITEMS 32 64 128)
foreach (variant IN ITEMS "" "rvfi")
set(arch "rv${xlen}")
if (flen EQUAL 32)
string(APPEND arch "f")
else()
elseif (flen EQUAL 64)
string(APPEND arch "d")
else()
string(APPEND arch "q")
endif()
if (variant)
string(APPEND arch "_${variant}")
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2 changes: 1 addition & 1 deletion c_emulator/riscv_sail.h
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Expand Up @@ -62,7 +62,7 @@ extern mach_bits zmstatus;
extern mach_bits zmepc, zmtval;
extern mach_bits zsepc, zstval;

extern mach_bits zfloat_result, zfloat_fflags;
extern mach_bits zfloat_result, zfloat_result_high, zfloat_fflags;

struct zMcause {
mach_bits zMcause_chunk_0;
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