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generated internal conditional compilation gates #281
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Very nice improvement! |
Feature wise, I believe so. The list of peripherals and which MCU they are present on is fairly complete (based on the C HAL) and I can't see any major downsides outside of this being a somewhat obscure capability of the build script (and the peripheral list being somewhat long ofc). The style of the gating I am less sure on.
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previous check would not error if two were selected
Reaching this arm would imply things have gone very wrong
H has a couple of pins that are often reserved on many parts. Full port on some larger footprints I is only present on L49 and up in the larger footprints
It is likely the build script will be extended to cover other activities in future. Modularise early to keep things tidy
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Coming back to this after a few weeks away. Updated naming, cleaned up the build script with an eye toward future additions and generally just looking with fresh eyes Each gate group now has its own unique name rather than all using
Naming is still a little shaky but it made no sense to standardise the left side of the gate and I have no idea what I was thinking with that idea... |
closes #277
This uses a build script to generate internal conditional compilation gates. This allows keeping the cargo features clean, while internally being able to use readable checks like
or
#[cfg(condition = "peripheral_usart3")]
The build script is dependency free and simple (just names and a boolean condition) so there is basically no impact on compile time and very little to understand. Currently generates two sets of "conditions"
peripheral presense mapping is derived from the STM32 Cube repository. I chose to map all peripherals (even those present on every device) for maximum clarity. the peripheral name used is the lower case of the peripheral #define from that repository
suggestions on naming very welcome (I consider "condition" to be a placeholder)