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generated internal conditional compilation gates #281

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Commits on Feb 9, 2022

  1. move feature check into build.rs for correctness

    previous check would not error if two were selected
    Crzyrndm committed Feb 9, 2022
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  6. update serial gates

    Crzyrndm committed Feb 9, 2022
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  8. add RTC type3 gate

    Crzyrndm committed Feb 9, 2022
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  10. update i2c gates

    Crzyrndm committed Feb 9, 2022
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  11. gpio f/g

    Crzyrndm committed Feb 9, 2022
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  12. CAN pin gating

    Crzyrndm committed Feb 9, 2022
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  13. more GPIO F/G

    Crzyrndm committed Feb 9, 2022
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  14. unreachable instead of an (incorrect) register block

    Reaching this arm would imply things have gone very wrong
    Crzyrndm committed Feb 9, 2022
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  17. update lib.rs gating

    Crzyrndm committed Feb 9, 2022
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  19. add gpioh and gpioi

    H has a couple of pins that are often reserved on many parts. Full port
    on some larger footprints
    I is only present on L49 and up in the larger footprints
    Crzyrndm committed Feb 9, 2022
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  21. update spi gates

    Crzyrndm committed Feb 9, 2022
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  22. timer gates

    Crzyrndm committed Feb 9, 2022
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  23. fix l442 duplication

    Crzyrndm committed Feb 9, 2022
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  24. enable gates

    Crzyrndm committed Feb 9, 2022
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  25. fix spi gates

    Crzyrndm committed Feb 9, 2022
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  26. update signature gates

    Crzyrndm committed Feb 9, 2022
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  27. update rtc2 conditional

    Crzyrndm committed Feb 9, 2022
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  28. update watchdog conditional

    Crzyrndm committed Feb 9, 2022
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  29. add l485 to ci

    Crzyrndm committed Feb 9, 2022
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  30. split feature check and generation into a child module

    It is likely the build script will be extended to cover other activities in future. Modularise early to keep things tidy
    Crzyrndm committed Feb 9, 2022
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  32. Swap QSPI pins and remove conflicting/wrong implementations (stm32-rs…

    …#283)
    
    # Conflicts:
    #	src/qspi.rs
    DerFetzer authored and Crzyrndm committed Feb 9, 2022
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