[LoadStoreOpToLLVM] Improve the block io 2d load lowering for the case that maskConstancyVer < tileHeight.

[chengjunlu]

To improve the block IO 2D load lowering for the case that maskConstancyVer < tileHeight.
Move the register bases of the adjusted part of tile height to the place after the vBlocks.
That we can easily adjust the size of the tile height of the block io.

[Copilot]

Pull Request Overview

This PR improves the block IO 2D load lowering in the LoadStoreOpToLLVM pass to handle cases where maskConstancyVer < tileHeight. The key improvement is a register base rearrangement strategy that rotates register bases of the adjusted tile height portion to appear after vBlocks, enabling easier adjustment of tile height for block IO operations.

Key Changes:

• Enhanced mask constancy validation to handle vertical mask constancy less than tile height
• Added register base rearrangement logic using std::rotate to optimize memory layout
• Added MSVC compatibility for __builtin_clz and __builtin_ctz intrinsics

Reviewed Changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 6 comments.

File	Description
third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp	Core implementation: Added MSVC intrinsic compatibility, enhanced mask validation, and register rearrangement logic for tile height adjustment
test/TritonIntelGPU/tensor-pointer-load-block-2d.mlir	Added comprehensive test cases for different DPAS configurations and repCluster patterns to validate the improved lowering

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[Copilot]

Pull Request Overview

Copilot reviewed 2 out of 2 changed files in this pull request and generated 2 comments.

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[Copilot]

Pull Request Overview

Copilot reviewed 2 out of 2 changed files in this pull request and generated 2 comments.

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