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Toady every library for HDL generating/parsing/simulation implements custom API for working with HDL and for in memory circuit representation.

Development of such a tools is extremely time consuming task. Differences in internal representation in current libraries also makes sharing of the code between the libraries impossible. This means that the developers of "hardware mapping algorithms"/"simulators"/"code analysis software" has to always write they api for parsing and generating of the HDL language and it has to be always implemented again because it time it can not be separated from original project.

Many problems in HDL synthesis are NP-hard tasks and are also hard to implement. In order to be able to share circuit transformations and optimizations etc. we need to have unified API and internal representations or at least have conversion function for different hardware representations. This also greatly simplify current libraries because Verilog/VHDL parsing and generating is large code.

Existing internal representations in different projects

• abc https://github.com/berkeley-abc/abc
• FIRRTL https://github.com/freechipsproject/firrtl
• hwt https://github.com/Nic30/hwt
• ICARUS Verilog https://github.com/steveicarus/iverilog
• MyHdl https://github.com/myhdl/myhdl
• Verilator https://www.veripool.org/projects/verilator/wiki/Intro
• Yosys https://github.com/YosysHQ/yosys