ICARUS Verilog

ICARUS Verilog

ICARUS Verilog is a Verilog simulator and synthesis tool. It can export the intermediate format into many output formats.

• License: GPL-2.1
• GIT: https://github.com/steveicarus/iverilog
• Internal representation: Verilog AST and netlist
• Optimization alg. paradigm: simple walker

Internal representation

• tgt-* directories contains the modules for conversion to target language

• As iverilog was oritginally probably only simulator there are is not strong API for HDL manipulation. On some places AST and netlist is used elsewhere. AST and netlist implementation is fragmented in many files.