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NetlistDB
NetlistDB is library for circuit manipulation and generation.
- License: MIT
- Internal representation: netlist of statements/operators
- Optimization paradigm: database query/visitor
The NetlistDB allows simple analysis of the or modification of the circuit thanks to the polymorphism. The main class Netlist is the container of the Net, Netlist, Statement, FunctionCall objects and represents module in Verilog.
The Net object can be generated by methods of the Netlist and does have overriden operators to simplify the build of the expressions. The Net.id.hidden flag tells if the net should be visible in HDL or if it is only expression.
There are multiple statements. Statements does have cached sensitivity list, latching info, IO in it's properties.
All objects are bi-directionally connected and implementing virtual methods "backward" and "forward" also all objects derives from same virtual base.
The representation is build with the support of parallel processing.